Massively Parallel Dynamically Reconfigurable ...
Document type :
Communication dans un congrès avec actes
DOI :
Title :
Massively Parallel Dynamically Reconfigurable Multi-FPGA Computing System
Author(s) :
Viswanathan, Venkatasubramanian [Auteur]
Laboratoire d'Automatique, de Mécanique et d'Informatique industrielles et Humaines - UMR 8201 [LAMIH]
Dynamic Reconfigurable Massively Parallel Architectures and Languages [DREAMPAL]
Ben Atitallah, Rabie [Auteur]
Dynamic Reconfigurable Massively Parallel Architectures and Languages [DREAMPAL]
Laboratoire d'Automatique, de Mécanique et d'Informatique industrielles et Humaines - UMR 8201 [LAMIH]
Dekeyser, Jean-Luc [Auteur]
Dynamic Reconfigurable Massively Parallel Architectures and Languages [DREAMPAL]
Laboratoire d'Automatique, de Mécanique et d'Informatique industrielles et Humaines - UMR 8201 [LAMIH]
Dynamic Reconfigurable Massively Parallel Architectures and Languages [DREAMPAL]
Ben Atitallah, Rabie [Auteur]
Dynamic Reconfigurable Massively Parallel Architectures and Languages [DREAMPAL]
Laboratoire d'Automatique, de Mécanique et d'Informatique industrielles et Humaines - UMR 8201 [LAMIH]
Dekeyser, Jean-Luc [Auteur]
Dynamic Reconfigurable Massively Parallel Architectures and Languages [DREAMPAL]
Conference title :
IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2015
City :
Vancouver, BC
Country :
Canada
Start date of the conference :
2015-05-02
English keyword(s) :
Parallel and dynamic computing
Multi-FPGA
scalable architecture
parallel reconfiguration
Multi-FPGA
scalable architecture
parallel reconfiguration
HAL domain(s) :
Informatique [cs]/Systèmes embarqués
Informatique [cs]/Architectures Matérielles [cs.AR]
Informatique [cs]/Architectures Matérielles [cs.AR]
English abstract : [en]
High Performance Embedded Computing (HPEC) applications are becoming highly sophisticated as they capture and process real-time data from several sources. In addition, they should adapt their functionalities according to ...
Show more >High Performance Embedded Computing (HPEC) applications are becoming highly sophisticated as they capture and process real-time data from several sources. In addition, they should adapt their functionalities according to the operational environments. The inherent hardware parallelism that allows Single Program Multiple Data (SPMD) execution model, high-speed serial I/O and Dynamic Partial Reconfiguration (DPR) features make FPGAs a highly attractive solution. The problem with current generation reconfigurable HPEC systems is that, they are usually built to meet the needs of a specific application i.e., Lacks flexibility to upgrade hardware resources or adaptability to different applications. In order to address these challenges, we propose a scalable and modular multi-FPGA computing platform, with a parallel full-duplex customizable communication network, that redefines the computation, communication and reconfiguration paradigms in such applications. Furthermore, in order to adapt to real-time application constraints, we propose a parallel DPR model. It is well-traced on the execution model (SPMD), to reconfigure all or a subset of the computing nodes in parallel during runtime.Show less >
Show more >High Performance Embedded Computing (HPEC) applications are becoming highly sophisticated as they capture and process real-time data from several sources. In addition, they should adapt their functionalities according to the operational environments. The inherent hardware parallelism that allows Single Program Multiple Data (SPMD) execution model, high-speed serial I/O and Dynamic Partial Reconfiguration (DPR) features make FPGAs a highly attractive solution. The problem with current generation reconfigurable HPEC systems is that, they are usually built to meet the needs of a specific application i.e., Lacks flexibility to upgrade hardware resources or adaptability to different applications. In order to address these challenges, we propose a scalable and modular multi-FPGA computing platform, with a parallel full-duplex customizable communication network, that redefines the computation, communication and reconfiguration paradigms in such applications. Furthermore, in order to adapt to real-time application constraints, we propose a parallel DPR model. It is well-traced on the execution model (SPMD), to reconfigure all or a subset of the computing nodes in parallel during runtime.Show less >
Language :
Anglais
Peer reviewed article :
Oui
Audience :
Internationale
Popular science :
Non
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