Titre :

Massively Parallel Dynamically Reconfigurable Multi-FPGA Computing System

Auteur(s) :

Viswanathan, Venkatasubramanian [Auteur]
Laboratoire d'Automatique, de Mécanique et d'Informatique industrielles et Humaines - UMR 8201 [LAMIH]
Dynamic Reconfigurable Massively Parallel Architectures and Languages [DREAMPAL]
Ben Atitallah, Rabie [Auteur]
Dynamic Reconfigurable Massively Parallel Architectures and Languages [DREAMPAL]
Laboratoire d'Automatique, de Mécanique et d'Informatique industrielles et Humaines - UMR 8201 [LAMIH]
Dekeyser, Jean-Luc [Auteur]
Dynamic Reconfigurable Massively Parallel Architectures and Languages [DREAMPAL]

Titre de la manifestation scientifique :

IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2015

Ville :

Vancouver, BC

Pays :

Canada

Date de début de la manifestation scientifique :

2015-05-02

Mot(s)-clé(s) en anglais :

Parallel and dynamic computing
Multi-FPGA
scalable architecture
parallel reconfiguration

Discipline(s) HAL :

Informatique [cs]/Systèmes embarqués
Informatique [cs]/Architectures Matérielles [cs.AR]

Résumé en anglais : [en]

High Performance Embedded Computing (HPEC) applications are becoming highly sophisticated as they capture and process real-time data from several sources. In addition, they should adapt their functionalities according to ...
Lire la suite >High Performance Embedded Computing (HPEC) applications are becoming highly sophisticated as they capture and process real-time data from several sources. In addition, they should adapt their functionalities according to the operational environments. The inherent hardware parallelism that allows Single Program Multiple Data (SPMD) execution model, high-speed serial I/O and Dynamic Partial Reconfiguration (DPR) features make FPGAs a highly attractive solution. The problem with current generation reconfigurable HPEC systems is that, they are usually built to meet the needs of a specific application i.e., Lacks flexibility to upgrade hardware resources or adaptability to different applications. In order to address these challenges, we propose a scalable and modular multi-FPGA computing platform, with a parallel full-duplex customizable communication network, that redefines the computation, communication and reconfiguration paradigms in such applications. Furthermore, in order to adapt to real-time application constraints, we propose a parallel DPR model. It is well-traced on the execution model (SPMD), to reconfigure all or a subset of the computing nodes in parallel during runtime.Lire moins >

Langue :

Anglais

Comité de lecture :

Oui

Audience :

Internationale

Vulgarisation :

Non

Collections :

• Centre de Recherche en Informatique, Signal et Automatique de Lille (CRIStAL) - UMR 9189

Source :

Harvested from HAL