Modeling Networks-on-Chip at System Level ...
Document type :
Communication dans un congrès avec actes
Title :
Modeling Networks-on-Chip at System Level with the MARTE UML profile
Author(s) :
Elhaji, Majdi [Auteur]
Laboratoire d'Electronique et de Microélectronique [Monastir] [EμE]
Boulet, Pierre [Auteur correspondant]
Contributions of the Data parallelism to real time [DART]
Tourki, Rached [Auteur]
Laboratoire d'Electronique et de Microélectronique [Monastir] [EμE]
Zitouni, Abdelkrim [Auteur]
Laboratoire d'Electronique et de Microélectronique [Monastir] [EμE]
Dekeyser, Jean-Luc [Auteur]
Contributions of the Data parallelism to real time [DART]
Meftali, Samy [Auteur]
Contributions of the Data parallelism to real time [DART]
Laboratoire d'Electronique et de Microélectronique [Monastir] [EμE]
Boulet, Pierre [Auteur correspondant]

Contributions of the Data parallelism to real time [DART]
Tourki, Rached [Auteur]
Laboratoire d'Electronique et de Microélectronique [Monastir] [EμE]
Zitouni, Abdelkrim [Auteur]
Laboratoire d'Electronique et de Microélectronique [Monastir] [EμE]
Dekeyser, Jean-Luc [Auteur]

Contributions of the Data parallelism to real time [DART]
Meftali, Samy [Auteur]
Contributions of the Data parallelism to real time [DART]
Conference title :
M-BED'2011
City :
Grenoble
Country :
France
Start date of the conference :
2011-03-18
Publication date :
2011-03-18
HAL domain(s) :
Informatique [cs]/Systèmes embarqués
English abstract : [en]
The study of Networks on Chips (NoCs) is a research field that primarily addresses the global communication in Systems-on-Chip (SoCs). The selected topology and the routing algorithm play a prime role in the performance ...
Show more >The study of Networks on Chips (NoCs) is a research field that primarily addresses the global communication in Systems-on-Chip (SoCs). The selected topology and the routing algorithm play a prime role in the performance of NoC architectures. In order to handle the design complexity and meet the tight time-to-market constraints, it is important to automate most of these NoC design phases. The extension of the UML language called UML profile for MARTE (Modeling and Analysis of Real-Time and Embedded systems) specifies some concepts for model-based design and analysis of real time and embedded systems. This paper presents a MARTE based methodology for modeling concepts of NoC based architectures. It aims at improving the effectiveness of the MARTE standard by clarifying some notations and extending some definitions in the standard, in order to be able to model complex architectures like NoCs.Show less >
Show more >The study of Networks on Chips (NoCs) is a research field that primarily addresses the global communication in Systems-on-Chip (SoCs). The selected topology and the routing algorithm play a prime role in the performance of NoC architectures. In order to handle the design complexity and meet the tight time-to-market constraints, it is important to automate most of these NoC design phases. The extension of the UML language called UML profile for MARTE (Modeling and Analysis of Real-Time and Embedded systems) specifies some concepts for model-based design and analysis of real time and embedded systems. This paper presents a MARTE based methodology for modeling concepts of NoC based architectures. It aims at improving the effectiveness of the MARTE standard by clarifying some notations and extending some definitions in the standard, in order to be able to model complex architectures like NoCs.Show less >
Language :
Anglais
Peer reviewed article :
Oui
Audience :
Internationale
Popular science :
Non
Collections :
Source :
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