Title :

Implementation of ARTiS, an Asymmetric Real-Time Extension of SMP Linux

Author(s) :

Marquet, Philippe [Auteur]
Contributions of the Data parallelism to real time [DART]
Laboratoire d'Informatique Fondamentale de Lille [LIFL]
Piel, Éric [Auteur]
Contributions of the Data parallelism to real time [DART]
Laboratoire d'Informatique Fondamentale de Lille [LIFL]
Soula, Julien [Auteur]
Laboratoire d'Informatique Fondamentale de Lille [LIFL]
Dekeyser, Jean-Luc [Auteur]
Contributions of the Data parallelism to real time [DART]
Laboratoire d'Informatique Fondamentale de Lille [LIFL]

Conference title :

Sixth Realtime Linux Workshop

City :

Singapore

Start date of the conference :

2004-11

Publication date :

2004-11

HAL domain(s) :

Informatique [cs]/Calcul parallèle, distribué et partagé [cs.DC]
Informatique [cs]/Système d'exploitation [cs.OS]

English abstract : [en]

ARTiS is a real-time extension of GNU/Linux dedicated to SMP systems (Symmetric Multi-Processors). ARTiS divides the CPUs of an SMP system into two sets: real-time CPUs and non real-time CPUs. Real-time CPUs execute ...
Show more >ARTiS is a real-time extension of GNU/Linux dedicated to SMP systems (Symmetric Multi-Processors). ARTiS divides the CPUs of an SMP system into two sets: real-time CPUs and non real-time CPUs. Real-time CPUs execute preemptible code only, thus tasks running on these processors perform predictably. If a task wants to enter into a non-preemptible section of code on a real-time processor, ARTiS will automatically migrate this task to a non real-time processor. Furthermore, dedicated load-balancing strategies allow all the system's CPUs to be fully exploited. \par The purpose of this paper is to describe the basic API that has been specified to deploy real-time applications, and to present the current implementation of the ARTiS model, which was achieved through modifications of the 2.6 Linux kernel. The implementation is build around an automatic migration of tasks between real-time and non real-time processors and the use of a load-balancer. The basic function of those mechanisms is to move a task structure from one processor to another. A strong constraint of the implementation is the impossibility for the code running on an RT processor to share a lock or to wait after another processor.Show less >

Language :

Anglais

Peer reviewed article :

Oui

Audience :

Non spécifiée

Popular science :

Non

Collections :

• Centre de Recherche en Informatique, Signal et Automatique de Lille (CRIStAL) - UMR 9189

Source :

Harvested from HAL