Title :

Transconductance / Drain Current Based Sensitivity Analysis for Analog CMOS Integrated Circuits

Author(s) :

Ou, Jack [Auteur]
Sonoma State University [Rohnert Park]
Maris Ferreira, Pietro [Auteur]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]

Conference title :

IEEE New Circuits Syst. Conf. (NEWCAS)

City :

Paris

Country :

France

Start date of the conference :

2013-06-16

HAL domain(s) :

Sciences de l'ingénieur [physics]/Micro et nanotechnologies/Microélectronique
Sciences de l'ingénieur [physics]/Electronique

English abstract : [en]

Recent studies have shown that transistor variability and ageing phenomena are responsible for variation of transconductance (gm) and drain current (ID) in MOSFETs. It is therefore important to perform sensitivity analysis ...
Show more >Recent studies have shown that transistor variability and ageing phenomena are responsible for variation of transconductance (gm) and drain current (ID) in MOSFETs. It is therefore important to perform sensitivity analysis at the earliest design stage in order to minimize effects of ageing. It is however not trivial to perform sensitivity analysis analytically because the 1-V characteristics of modern transistors can not modeled without using complicated expressions. In this paper, We propose a technique that utilizes the transconductance-to-drain current ratio (gm/ID) of a transistor to captures the sensitivity of a circuit. This technique is applicable to transistors biased in all regions of operations. To explore the effectiveness of the proposed technique in practical circuit design, the sensitivity of a common source amplifier is analyzed. The proposed technique has an accuracy of ± 15 % between 4 <; gm/ID<; 28.Show less >

Language :

Anglais

Peer reviewed article :

Oui

Audience :

Internationale

Popular science :

Non

Collections :

• Institut d'Électronique, de Microélectronique et de Nanotechnologie (IEMN) - UMR 8520

Source :

Harvested from HAL