Model based design flow for implementing ...
Type de document :
Communication dans un congrès avec actes
Titre :
Model based design flow for implementing an Anti-Collision Radar detection system
Auteur(s) :
Quadri, Imran Rafiq [Auteur]
Contributions of the Data parallelism to real time [DART]
El Hillali, Yassin [Auteur]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
Meftali, Samy [Auteur]
Contributions of the Data parallelism to real time [DART]
Laboratoire d'Informatique Fondamentale de Lille [LIFL]
Dekeyser, Jean-Luc [Auteur]
Contributions of the Data parallelism to real time [DART]
Laboratoire d'Informatique Fondamentale de Lille [LIFL]
Contributions of the Data parallelism to real time [DART]
El Hillali, Yassin [Auteur]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
Meftali, Samy [Auteur]
Contributions of the Data parallelism to real time [DART]
Laboratoire d'Informatique Fondamentale de Lille [LIFL]
Dekeyser, Jean-Luc [Auteur]
Contributions of the Data parallelism to real time [DART]
Laboratoire d'Informatique Fondamentale de Lille [LIFL]
Titre de la manifestation scientifique :
9th International IEEE Conference on ITS Telecommunications (ITS-T 2009)
Ville :
Lille
Pays :
France
Date de début de la manifestation scientifique :
2009-10-20
Date de publication :
2009-10-20
Discipline(s) HAL :
Informatique [cs]/Systèmes embarqués
Résumé en anglais : [en]
In order to ensure and increase the safety and reliability of transport systems, these systems are becoming more and more intelligent. They integrate more and more sensors and communication systems. Each of these functionalities ...
Lire la suite >In order to ensure and increase the safety and reliability of transport systems, these systems are becoming more and more intelligent. They integrate more and more sensors and communication systems. Each of these functionalities can be implemented on a System-on-Chip (SoC). These functionalities are carried out by massive computations. As the number of integrated functionalities increase in the transport systems, the design and implementation complexity also increases at a tremendous rate. Implementation of these functionalities can be carried out either via FPGAs or DSP (digital signal processors) platforms. FPGAs are considered the ideal choice as they accelerate the computations by executing the algorithms in a parallel manner. Actually the initial steps in existing design flows are the development of the complex algorithms; and then their manual implementation, which are daunting tasks. Change in the scale of the algorithm requires starting the implementation over from scratch which results in increase design time. Normally these steps are carried out by teams of different domains which could result in compatibility issues. We propose a high abstraction level design methodology for implementation of these algorithms in a graphical manner. The advantages offered by our approach aim to reduce time to make up or time to market. Changes in the nature of the algorithm can be easily carried out due to their graphical nature and the code can be generated automatically rapidly. Afterwards the implementation can be carried out on the target FPGA platforms.Lire moins >
Lire la suite >In order to ensure and increase the safety and reliability of transport systems, these systems are becoming more and more intelligent. They integrate more and more sensors and communication systems. Each of these functionalities can be implemented on a System-on-Chip (SoC). These functionalities are carried out by massive computations. As the number of integrated functionalities increase in the transport systems, the design and implementation complexity also increases at a tremendous rate. Implementation of these functionalities can be carried out either via FPGAs or DSP (digital signal processors) platforms. FPGAs are considered the ideal choice as they accelerate the computations by executing the algorithms in a parallel manner. Actually the initial steps in existing design flows are the development of the complex algorithms; and then their manual implementation, which are daunting tasks. Change in the scale of the algorithm requires starting the implementation over from scratch which results in increase design time. Normally these steps are carried out by teams of different domains which could result in compatibility issues. We propose a high abstraction level design methodology for implementation of these algorithms in a graphical manner. The advantages offered by our approach aim to reduce time to make up or time to market. Changes in the nature of the algorithm can be easily carried out due to their graphical nature and the code can be generated automatically rapidly. Afterwards the implementation can be carried out on the target FPGA platforms.Lire moins >
Langue :
Anglais
Comité de lecture :
Oui
Audience :
Internationale
Vulgarisation :
Non
Source :
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