Very low Schottky barrier to n-type silicon ...
Document type :
Compte-rendu et recension critique d'ouvrage
Title :
Very low Schottky barrier to n-type silicon with PtEr-stack silicide
Author(s) :
Tang, Xing [Auteur]
Université Catholique de Louvain = Catholic University of Louvain [UCL]
Katcki, J. [Auteur]
Dubois, Emmanuel [Auteur]
Microélectronique Silicium - IEMN [MICROELEC SI - IEMN]
Reckinger, N. [Auteur]
Université Catholique de Louvain = Catholic University of Louvain [UCL]
Ratajczak, J. [Auteur]
Larrieu, G. [Auteur]
Microélectronique Silicium - IEMN [MICROELEC SI - IEMN]
Loumaye, P. [Auteur]
Université Catholique de Louvain = Catholic University of Louvain [UCL]
Nisole, O. [Auteur]
Université Catholique de Louvain = Catholic University of Louvain [UCL]
Bayot, V. [Auteur]
Université Catholique de Louvain = Catholic University of Louvain [UCL]
Université Catholique de Louvain = Catholic University of Louvain [UCL]
Katcki, J. [Auteur]
Dubois, Emmanuel [Auteur]

Microélectronique Silicium - IEMN [MICROELEC SI - IEMN]
Reckinger, N. [Auteur]
Université Catholique de Louvain = Catholic University of Louvain [UCL]
Ratajczak, J. [Auteur]
Larrieu, G. [Auteur]
Microélectronique Silicium - IEMN [MICROELEC SI - IEMN]
Loumaye, P. [Auteur]
Université Catholique de Louvain = Catholic University of Louvain [UCL]
Nisole, O. [Auteur]
Université Catholique de Louvain = Catholic University of Louvain [UCL]
Bayot, V. [Auteur]
Université Catholique de Louvain = Catholic University of Louvain [UCL]
Journal title :
Solid-State Electronics
Pages :
2105-2111
Publisher :
Elsevier
Publication date :
2003
ISSN :
0038-1101
English keyword(s) :
Schottky barrier MOSFET
PtEr-stack silicide system
Rapid thermal annealing
Schottky barrier height
Silicon series resistance
PtEr-stack silicide system
Rapid thermal annealing
Schottky barrier height
Silicon series resistance
HAL domain(s) :
Sciences de l'ingénieur [physics]/Electronique
English abstract : [en]
We investigate Er silicide formed on n-type silicon. In order to protect the Er from oxidation during the formation of Er silicide in non-UHV conditions, a Pt layer is deposed successively on top of Er layer. Surprisingly, ...
Show more >We investigate Er silicide formed on n-type silicon. In order to protect the Er from oxidation during the formation of Er silicide in non-UHV conditions, a Pt layer is deposed successively on top of Er layer. Surprisingly, we observe that Pt remains essentially unaffected in the formation of Er silicide at temperatures lower than 700°C. We find that silicidation process is fully completed by rapid thermal annealing at 500°C. A simplified method of analysis considering the final Schottky barrier MOSFET application has been used to characterize the Schottky barrier of the PtEr-stack silicide system. A very low apparent Schottky barrier (smaller than 0.1 eV) on a n-type silicon substrate with a concentration of 1.4 × 10$^{16}$ cm$^{−3}$ in the active region has been obtained.Show less >
Show more >We investigate Er silicide formed on n-type silicon. In order to protect the Er from oxidation during the formation of Er silicide in non-UHV conditions, a Pt layer is deposed successively on top of Er layer. Surprisingly, we observe that Pt remains essentially unaffected in the formation of Er silicide at temperatures lower than 700°C. We find that silicidation process is fully completed by rapid thermal annealing at 500°C. A simplified method of analysis considering the final Schottky barrier MOSFET application has been used to characterize the Schottky barrier of the PtEr-stack silicide system. A very low apparent Schottky barrier (smaller than 0.1 eV) on a n-type silicon substrate with a concentration of 1.4 × 10$^{16}$ cm$^{−3}$ in the active region has been obtained.Show less >
Language :
Anglais
Popular science :
Non
Source :
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