Virtual Platform to Analyze the Security ...
Type de document :
Communication dans un congrès avec actes
Titre :
Virtual Platform to Analyze the Security of a System on Chip at Microarchitectural Level
Auteur(s) :
Forcioli, Quentin [Auteur]
Secure and Safe Hardware [SSH]
Département Communications & Electronique [COMELEC]
Institut Polytechnique de Paris [IP Paris]
Laboratoire Traitement et Communication de l'Information [LTCI]
Danger, Jean-Luc [Auteur]
Laboratoire Traitement et Communication de l'Information [LTCI]
Secure and Safe Hardware [SSH]
Département Communications & Electronique [COMELEC]
Institut Polytechnique de Paris [IP Paris]
Maurice, Clementine [Auteur]
Self-adaptation for distributed services and large software systems [SPIRALS]
Bossuet, Lilian [Auteur]
Laboratoire Hubert Curien [LHC]
Bruguier, Florent [Auteur]
ADAptive Computing [ADAC]
Mushtaq, Maria [Auteur]
ADAptive Computing [ADAC]
Novo, David [Auteur]
ADAptive Computing [ADAC]
France, Loïc [Auteur]
ADAptive Computing [ADAC]
Benoit, Pascal [Auteur]
ADAptive Computing [ADAC]
Guilley, Sylvain [Auteur]
Secure and Safe Hardware [SSH]
Département Communications & Electronique [COMELEC]
Institut Polytechnique de Paris [IP Paris]
Secure-IC S.A.S
Perianin, Thomas [Auteur]
Secure-IC S.A.S
Secure and Safe Hardware [SSH]
Département Communications & Electronique [COMELEC]
Institut Polytechnique de Paris [IP Paris]
Laboratoire Traitement et Communication de l'Information [LTCI]
Danger, Jean-Luc [Auteur]
Laboratoire Traitement et Communication de l'Information [LTCI]
Secure and Safe Hardware [SSH]
Département Communications & Electronique [COMELEC]
Institut Polytechnique de Paris [IP Paris]
Maurice, Clementine [Auteur]
Self-adaptation for distributed services and large software systems [SPIRALS]
Bossuet, Lilian [Auteur]
Laboratoire Hubert Curien [LHC]
Bruguier, Florent [Auteur]
ADAptive Computing [ADAC]
Mushtaq, Maria [Auteur]
ADAptive Computing [ADAC]
Novo, David [Auteur]
ADAptive Computing [ADAC]
France, Loïc [Auteur]
ADAptive Computing [ADAC]
Benoit, Pascal [Auteur]
ADAptive Computing [ADAC]
Guilley, Sylvain [Auteur]
Secure and Safe Hardware [SSH]
Département Communications & Electronique [COMELEC]
Institut Polytechnique de Paris [IP Paris]
Secure-IC S.A.S
Perianin, Thomas [Auteur]
Secure-IC S.A.S
Titre de la manifestation scientifique :
EuroS&PW 2021 - IEEE European Symposium on Security and Privacy Workshops
Ville :
Vienne
Pays :
Autriche
Date de début de la manifestation scientifique :
2021-09-06
Date de publication :
2021
Mot(s)-clé(s) en anglais :
Security
Microarchitecture
Simulation
gem5
SoC
Microarchitecture
Simulation
gem5
SoC
Discipline(s) HAL :
Informatique [cs]/Cryptographie et sécurité [cs.CR]
Résumé en anglais : [en]
The processors (CPUs) embedded in System on Chip (SoC) have to face recent attacks taking advantage of vulnerabilities/features in their microarchitectures to retrieve secret information. Indeed, the increase in complexity ...
Lire la suite >The processors (CPUs) embedded in System on Chip (SoC) have to face recent attacks taking advantage of vulnerabilities/features in their microarchitectures to retrieve secret information. Indeed, the increase in complexity of modern CPU and SoC is mainly driven by the seek of performance rather than security. Even if efforts like isolation techniques have been taken to thwart cyberattacks, most microarchitectural features can open the door to security holes. One typical example is the exploitation of cache memory which keeps track of the program execution and paves the way to side-channel (SCA) analysis and transient execution attacks like Meltdown and Spectre, which take advantage of speculative execution. This paper introduces an ongoing study aiming at analyzing the attacks relying on the hardware vulnerabilities of the microarchitectures of CPUs and SoCs. The main objective is to create a virtual and open platform that simulates the behavior of microarchitectural features and their interactions with the peripherals, like accelerators and memories in emerging technologies. The gem5 simulator, whose configuration can be customized to a specific CPU or SoC architecture, is the basis of our chosen platform for security analysis.Lire moins >
Lire la suite >The processors (CPUs) embedded in System on Chip (SoC) have to face recent attacks taking advantage of vulnerabilities/features in their microarchitectures to retrieve secret information. Indeed, the increase in complexity of modern CPU and SoC is mainly driven by the seek of performance rather than security. Even if efforts like isolation techniques have been taken to thwart cyberattacks, most microarchitectural features can open the door to security holes. One typical example is the exploitation of cache memory which keeps track of the program execution and paves the way to side-channel (SCA) analysis and transient execution attacks like Meltdown and Spectre, which take advantage of speculative execution. This paper introduces an ongoing study aiming at analyzing the attacks relying on the hardware vulnerabilities of the microarchitectures of CPUs and SoCs. The main objective is to create a virtual and open platform that simulates the behavior of microarchitectural features and their interactions with the peripherals, like accelerators and memories in emerging technologies. The gem5 simulator, whose configuration can be customized to a specific CPU or SoC architecture, is the basis of our chosen platform for security analysis.Lire moins >
Langue :
Anglais
Comité de lecture :
Oui
Audience :
Internationale
Vulgarisation :
Non
Collections :
Source :
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