Register file reliability enhancement ...
Type de document :
Communication dans un congrès avec actes
Titre :
Register file reliability enhancement through adjacent narrow-width exploitation.
Auteur(s) :
Ahangari, Hamzeh [Auteur]
Universite Bilkent [Ankara]
Alouani, Lihsen [Auteur]
COMmunications NUMériques - IEMN [COMNUM - IEMN]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
Özturk, Özcan [Auteur]
Universite Bilkent [Ankara]
Niar, Smail [Auteur]
Laboratoire d'Automatique, de Mécanique et d'Informatique industrielles et Humaines - UMR 8201 [LAMIH]
Rivenq, Atika [Auteur]
COMmunications NUMériques - IEMN [COMNUM - IEMN]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
Universite Bilkent [Ankara]
Alouani, Lihsen [Auteur]
COMmunications NUMériques - IEMN [COMNUM - IEMN]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
Özturk, Özcan [Auteur]
Universite Bilkent [Ankara]
Niar, Smail [Auteur]
Laboratoire d'Automatique, de Mécanique et d'Informatique industrielles et Humaines - UMR 8201 [LAMIH]
Rivenq, Atika [Auteur]
COMmunications NUMériques - IEMN [COMNUM - IEMN]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
Titre de la manifestation scientifique :
2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS)
Ville :
Istanbul
Pays :
Turquie
Date de début de la manifestation scientifique :
2016-04-12
Titre de l’ouvrage :
2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS)
Éditeur :
IEEE
Mot(s)-clé(s) en anglais :
"Registers"
Radio frequency
Computer architecture
Microprocessors
Integrated circuit reliability
SRAM cells
Radio frequency
Computer architecture
Microprocessors
Integrated circuit reliability
SRAM cells
Discipline(s) HAL :
Informatique [cs]
Sciences de l'ingénieur [physics]
Sciences de l'ingénieur [physics]
Résumé en anglais : [en]
Due to the increasing vulnerability of CMOS circuits, new generations of microprocessors require an inevitable focus on reliability issues. As the Register File (RF) constitutes a critical element within the processor ...
Lire la suite >Due to the increasing vulnerability of CMOS circuits, new generations of microprocessors require an inevitable focus on reliability issues. As the Register File (RF) constitutes a critical element within the processor pipeline, it is mandatory to enhance the RF reliability to develop fault tolerant architectures. This paper proposes Adjacent Register Hardened RF (ARH), a new RF architecture that exploits the adjacent byte-level narrow-width values for hardening registers at runtime. Registers are paired together by some special switches referred to as joiners. Dummy sign bits of each register are used to keep redundant data of its counterpart register. We use 7T/14T SRAM cell [6] to combine redundant bits together to make a single bit cell which is, by far, more resilient against faults. Our simulations show that with 3% to 12% power overhead and 10% to 20% increase in area, in comparison to baseline RF, we can obtain up to 80% reduction in soft error rate (SER).Lire moins >
Lire la suite >Due to the increasing vulnerability of CMOS circuits, new generations of microprocessors require an inevitable focus on reliability issues. As the Register File (RF) constitutes a critical element within the processor pipeline, it is mandatory to enhance the RF reliability to develop fault tolerant architectures. This paper proposes Adjacent Register Hardened RF (ARH), a new RF architecture that exploits the adjacent byte-level narrow-width values for hardening registers at runtime. Registers are paired together by some special switches referred to as joiners. Dummy sign bits of each register are used to keep redundant data of its counterpart register. We use 7T/14T SRAM cell [6] to combine redundant bits together to make a single bit cell which is, by far, more resilient against faults. Our simulations show that with 3% to 12% power overhead and 10% to 20% increase in area, in comparison to baseline RF, we can obtain up to 80% reduction in soft error rate (SER).Lire moins >
Langue :
Anglais
Comité de lecture :
Oui
Audience :
Internationale
Vulgarisation :
Non
Source :
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