Coarse/fine delay element design in 28 nm FD-SOI
Document type :
Partie d'ouvrage
Title :
Coarse/fine delay element design in 28 nm FD-SOI
Author(s) :
Sourikopoulos, Ilias [Auteur]
Institut de Recherche sur les Composants logiciels et matériels pour l'Information et la Communication Avancé - UAR 3380 [IRCICA]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
Cathelin, Andreia [Auteur]
STMicroelectronics [Crolles] [ST-CROLLES]
Kaiser, Andreas [Auteur]
Microélectronique Silicium - IEMN [MICROELEC SI - IEMN]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
Frappe, Antoine [Auteur]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
Microélectronique Silicium - IEMN [MICROELEC SI - IEMN]
Institut de Recherche sur les Composants logiciels et matériels pour l'Information et la Communication Avancé - UAR 3380 [IRCICA]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
Cathelin, Andreia [Auteur]
STMicroelectronics [Crolles] [ST-CROLLES]
Kaiser, Andreas [Auteur]
Microélectronique Silicium - IEMN [MICROELEC SI - IEMN]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
Frappe, Antoine [Auteur]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
Microélectronique Silicium - IEMN [MICROELEC SI - IEMN]
Book title :
The Fourth Terminal
Publisher :
Springer International Publishing
Publication place :
Cham
Publication date :
2020-04-26
ISBN :
ISBN 978-3-030-39495-0 ; eISBN 978-3-030-39496-7
English keyword(s) :
Delay element
Delay line
Current-starving
Thyristor
Schmitt trigger
Short-circuit current
Delay line
Current-starving
Thyristor
Schmitt trigger
Short-circuit current
HAL domain(s) :
Sciences de l'ingénieur [physics]
English abstract : [en]
This chapter starts by highlighting the requirements and existing techniques in producing digital delay, summarizing the state of the art. Subsequently, a topology assessment is presented based on specified performance ...
Show more >This chapter starts by highlighting the requirements and existing techniques in producing digital delay, summarizing the state of the art. Subsequently, a topology assessment is presented based on specified performance metrics. The proposed delay cell which was designed, fabricated, and characterized is then described. Specifically, the proposed design is based on a topology with low-supply-noise sensitivity and low jitter. Functionality is extended to support coarse/fine control for the output delay value, without the need for additional hardware. This is made possible by taking advantage of the body-biasing capabilities available in FD-SOI technology. The proposed delay element presents unique performance characteristics in terms of the achieved delay resolution and delay dynamic range. The chapter concludes with the demonstration of a delay line prototype, fabricated in ST 28 nm FD-SOI technology. After a general overview of delay techniques the proposed topology is described, by focusing on the major design aspects. Measurement results are then presented and a short discussion follows on the characterization findings.Show less >
Show more >This chapter starts by highlighting the requirements and existing techniques in producing digital delay, summarizing the state of the art. Subsequently, a topology assessment is presented based on specified performance metrics. The proposed delay cell which was designed, fabricated, and characterized is then described. Specifically, the proposed design is based on a topology with low-supply-noise sensitivity and low jitter. Functionality is extended to support coarse/fine control for the output delay value, without the need for additional hardware. This is made possible by taking advantage of the body-biasing capabilities available in FD-SOI technology. The proposed delay element presents unique performance characteristics in terms of the achieved delay resolution and delay dynamic range. The chapter concludes with the demonstration of a delay line prototype, fabricated in ST 28 nm FD-SOI technology. After a general overview of delay techniques the proposed topology is described, by focusing on the major design aspects. Measurement results are then presented and a short discussion follows on the characterization findings.Show less >
Language :
Anglais
Audience :
Internationale
Popular science :
Non
Source :