Trade-off Exploration for Target Tracking ...
Type de document :
Pré-publication ou Document de travail
Titre :
Trade-off Exploration for Target Tracking Application in a Customized Multiprocessor Architecture
Auteur(s) :
Khan, Jehangir [Auteur]
Laboratoire d'Automatique, de Mécanique et d'Informatique industrielles et Humaines - UMR 8201 [LAMIH]
Niar, Smail [Auteur]
Laboratoire d'Automatique, de Mécanique et d'Informatique industrielles et Humaines - UMR 8201 [LAMIH]
Saghir, Mazen [Auteur]
Department of Computer Science and Engineering [Texas A&M University] [CSE]
Rivenq, Atika [Auteur]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
El Hillali, Yassin [Auteur]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
Laboratoire d'Automatique, de Mécanique et d'Informatique industrielles et Humaines - UMR 8201 [LAMIH]
Niar, Smail [Auteur]
Laboratoire d'Automatique, de Mécanique et d'Informatique industrielles et Humaines - UMR 8201 [LAMIH]
Saghir, Mazen [Auteur]
Department of Computer Science and Engineering [Texas A&M University] [CSE]
Rivenq, Atika [Auteur]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
El Hillali, Yassin [Auteur]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
Discipline(s) HAL :
Informatique [cs]/Architectures Matérielles [cs.AR]
Sciences de l'ingénieur [physics]/Electronique
Sciences de l'ingénieur [physics]/Traitement du signal et de l'image [eess.SP]
Informatique [cs]/Traitement du signal et de l'image [eess.SP]
Sciences de l'ingénieur [physics]/Electronique
Sciences de l'ingénieur [physics]/Traitement du signal et de l'image [eess.SP]
Informatique [cs]/Traitement du signal et de l'image [eess.SP]
Résumé en anglais : [en]
This paper presents the design of an FPGA-based multiprocessor-system-on-chip (MPSoC) architecture optimized for Multiple Target Tracking (MTT) in automotive applications. An MTT system uses an automotive radar to track ...
Lire la suite >This paper presents the design of an FPGA-based multiprocessor-system-on-chip (MPSoC) architecture optimized for Multiple Target Tracking (MTT) in automotive applications. An MTT system uses an automotive radar to track the speed and relative position of all the vehicles (targets) within its field of view. As the number of targets increases, the computational needs of the MTT system also increasemaking it difficult for a single processor to handle it alone. Our implementation distributes the computational load among multiple soft processor cores optimized for executing specific computational tasks. The paper explains how we designed and profiled the MTT application to partition it among different processors. It also explains how we applied different optimizations to customize the individual processor cores to their assigned tasks and to assess their impact on performance and FPGA resource utilization. The result is a complete MTT application running on an optimized MPSoC architecture that fits in a contemporary medium-sized FPGA and that meets the application's real-time constraints.Lire moins >
Lire la suite >This paper presents the design of an FPGA-based multiprocessor-system-on-chip (MPSoC) architecture optimized for Multiple Target Tracking (MTT) in automotive applications. An MTT system uses an automotive radar to track the speed and relative position of all the vehicles (targets) within its field of view. As the number of targets increases, the computational needs of the MTT system also increasemaking it difficult for a single processor to handle it alone. Our implementation distributes the computational load among multiple soft processor cores optimized for executing specific computational tasks. The paper explains how we designed and profiled the MTT application to partition it among different processors. It also explains how we applied different optimizations to customize the individual processor cores to their assigned tasks and to assess their impact on performance and FPGA resource utilization. The result is a complete MTT application running on an optimized MPSoC architecture that fits in a contemporary medium-sized FPGA and that meets the application's real-time constraints.Lire moins >
Langue :
Anglais
Source :
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