Imperfect Return Path Effects on RLCG Model ...
Document type :
Communication dans un congrès avec actes
DOI :
Title :
Imperfect Return Path Effects on RLCG Model of Single and Coupled Interconnects: Propagation Delay, Rise Time and Crosstalk Prediction
Author(s) :
Legier, Jean-François [Auteur]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
Paleczny, Erick [Auteur]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
El Bouazzati, K. [Auteur]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
Deschacht, Denis [Auteur]
Conception et Test de Systèmes MICroélectroniques [SysMIC]
Huret, Fabrice [Auteur]
Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (UMR 3192) [Lab-STICC]
Laboratoire d'Electronique et Systèmes de Télécommunications [LEST]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
Paleczny, Erick [Auteur]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
El Bouazzati, K. [Auteur]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
Deschacht, Denis [Auteur]
Conception et Test de Systèmes MICroélectroniques [SysMIC]
Huret, Fabrice [Auteur]
Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (UMR 3192) [Lab-STICC]
Laboratoire d'Electronique et Systèmes de Télécommunications [LEST]
Conference title :
SPI: Signal Propagation on Interconnects
City :
Pisa
Country :
Italie
Start date of the conference :
2002-06-12
Book title :
6th IEEE Workshop on Signal Propagation on Interconnects
Publication date :
2002
English keyword(s) :
Predictive models
HAL domain(s) :
Sciences de l'ingénieur [physics]/Traitement du signal et de l'image [eess.SP]
English abstract : [en]
If we take a look at the latest ITRS 2001 edition[1], we will realize the number and difficulties of technical challenges the semiconductor industry must solve. Traditional scaling which has been at the basis of the semi ...
Show more >If we take a look at the latest ITRS 2001 edition[1], we will realize the number and difficulties of technical challenges the semiconductor industry must solve. Traditional scaling which has been at the basis of the semi conductor industry during these last three decades is indeed beginning to show limits in CMOS planar process as well as in connecting each elementary active device. The new edition roadmap highlight the need of modeling lithography technology, deposition and etch variation across a wafer, and simulating gate stack and ultra shallow dopant distributions, and junctions. Extensive studies are also required in high frequency circuit modeling. Efficient simulation of full chip interconnect delay is also needed as well as 3D transmission line interconnect simulation.Show less >
Show more >If we take a look at the latest ITRS 2001 edition[1], we will realize the number and difficulties of technical challenges the semiconductor industry must solve. Traditional scaling which has been at the basis of the semi conductor industry during these last three decades is indeed beginning to show limits in CMOS planar process as well as in connecting each elementary active device. The new edition roadmap highlight the need of modeling lithography technology, deposition and etch variation across a wafer, and simulating gate stack and ultra shallow dopant distributions, and junctions. Extensive studies are also required in high frequency circuit modeling. Efficient simulation of full chip interconnect delay is also needed as well as 3D transmission line interconnect simulation.Show less >
Language :
Anglais
Peer reviewed article :
Oui
Audience :
Internationale
Popular science :
Non
Source :