Title :

Design optimization of AlInAs-GaInAs HEMTs for low-noise applications

Author(s) :

Mateos, Javier [Auteur]
Universidad de Salamanca [España] = University of Salamanca [Spain]
González, Tomás [Auteur]
Universidad de Salamanca [España] = University of Salamanca [Spain]
Pardo, Daniel [Auteur]
Universidad de Salamanca [España] = University of Salamanca [Spain]
Bollaert, Sylvain [Auteur]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
Parenty, Thierry [Auteur]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
Cappy, Alain [Auteur]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]

Journal title :

IEEE Transactions on Electron Devices

Pages :

1228-1233

Publisher :

Institute of Electrical and Electronics Engineers

Publication date :

2004-08

ISSN :

0018-9383

English keyword(s) :

Semiconductor device modeling
Semiconductor device noise
Semiconductor device doping
Monte Carlo methods
Optimization methods
Resistance
Capacitance
Aluminum compounds
Gallium compounds
MODFETs

HAL domain(s) :

Sciences de l'ingénieur [physics]

English abstract : [en]

In order to optimize the low-noise performance of 50-nm-gate AlInAs-GalnAs high-electron mobility transistors (HEMTs), by using an ensemble Monte Carlo simulation we study the influence of three important technological ...
Show more >In order to optimize the low-noise performance of 50-nm-gate AlInAs-GalnAs high-electron mobility transistors (HEMTs), by using an ensemble Monte Carlo simulation we study the influence of three important technological parameters on their noise level: the doping of the /spl delta/-doped layer, the width of the devices and the length of the recess. The noise behavior of the devices is firstly analyzed in terms of the physics-based P, R, and C parameters, and then characterized from a practical (circuit oriented) point of view through their four noise parameters: minimum noise figure, F/sub min/, noise resistance, R/sub n/, and complex input admittance, Y/sub opt/ (or reflection coefficient, /spl Gamma//sub opt/). We have observed an enhancement of the noise when the /spl delta/-doping or the device width are increased (a deterioration parallel to that of f/sub max/). Thus, the optimum noise operation is obtained for the lowest possible values of the /spl delta/-doping and device width. However, for small width the effect of the offset parasitic capacitances makes F/sub min/ increase, thus, imposing a limit for the reduction of the noise. Moreover, the increase of R/sub n/ for small W makes the noise tuning condition critical to reach the optimum low-noise operation. We have also confirmed that when shortening the recess length from 100 to 20 nm at each side of the gate F/sub min/ is reduced, with a slight deterioration of f/sub max/, while the static characteristics are not modified.Show less >

Language :

Anglais

Peer reviewed article :

Oui

Audience :

Internationale

Popular science :

Non

Collections :

• Institut d'Électronique, de Microélectronique et de Nanotechnologie (IEMN) - UMR 8520

Source :

Harvested from HAL