Analysis and modeling of substrate impedance ...
Type de document :
Communication dans un congrès avec actes
Titre :
Analysis and modeling of substrate impedance network in RF CMOS
Auteur(s) :
Bouhana, Emmanuel [Auteur]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
STMicroelectronics [Crolles] [ST-CROLLES]
Scheerer, Patrick [Auteur]
STMicroelectronics [Crolles] [ST-CROLLES]
Boret, Samuel [Auteur]
STMicroelectronics [Crolles] [ST-CROLLES]
Gloria, Daniel [Auteur]
STMicroelectronics [Crolles] [ST-CROLLES]
Dambrine, Gilles [Auteur]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
Minondo, Michel [Auteur]
STMicroelectronics [Crolles] [ST-CROLLES]
Jaouen, Hervé [Auteur]
STMicroelectronics [Crolles] [ST-CROLLES]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
STMicroelectronics [Crolles] [ST-CROLLES]
Scheerer, Patrick [Auteur]
STMicroelectronics [Crolles] [ST-CROLLES]
Boret, Samuel [Auteur]
STMicroelectronics [Crolles] [ST-CROLLES]
Gloria, Daniel [Auteur]
STMicroelectronics [Crolles] [ST-CROLLES]
Dambrine, Gilles [Auteur]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
Minondo, Michel [Auteur]
STMicroelectronics [Crolles] [ST-CROLLES]
Jaouen, Hervé [Auteur]
STMicroelectronics [Crolles] [ST-CROLLES]
Titre de la manifestation scientifique :
IEEE International Conference on Microelectronic Test Structures
Ville :
Austin, TX
Pays :
Etats-Unis d'Amérique
Date de début de la manifestation scientifique :
2006-03-06
Titre de l’ouvrage :
Proceedings of the 2006 IEEE International Conference on Microelectronic Test Structures, ICMTS
Éditeur :
IEEE, Piscataway, NJ, USA
Date de publication :
2006
Mot(s)-clé(s) en anglais :
Semiconductor device modeling
Impedance
Intelligent networks
Radio frequency
Capacitance
Plugs
Isolation technology
Fingers
CMOS technology
MOSFET circuits
Impedance
Intelligent networks
Radio frequency
Capacitance
Plugs
Isolation technology
Fingers
CMOS technology
MOSFET circuits
Discipline(s) HAL :
Sciences de l'ingénieur [physics]
Résumé en anglais : [en]
This paper presents a new approach for analyzing and modeling the substrate impedance network in RF CMOS. Thanks to preliminary and proper de-embedding of known parasitics, the substrate network is directly identified. ...
Lire la suite >This paper presents a new approach for analyzing and modeling the substrate impedance network in RF CMOS. Thanks to preliminary and proper de-embedding of known parasitics, the substrate network is directly identified. Using this approach on MOS transistors from 130 down to 65 nm technologies allows to point out the respective implications of the isolation layer and the surrounding well plug on high-frequency characteristics. Their impacts are studied and a new model is proposed.Lire moins >
Lire la suite >This paper presents a new approach for analyzing and modeling the substrate impedance network in RF CMOS. Thanks to preliminary and proper de-embedding of known parasitics, the substrate network is directly identified. Using this approach on MOS transistors from 130 down to 65 nm technologies allows to point out the respective implications of the isolation layer and the surrounding well plug on high-frequency characteristics. Their impacts are studied and a new model is proposed.Lire moins >
Langue :
Anglais
Comité de lecture :
Oui
Audience :
Internationale
Vulgarisation :
Non
Source :