Hierarchical Graph-Based Sizing for Analog ...
Type de document :
Communication dans un congrès avec actes
DOI :
Titre :
Hierarchical Graph-Based Sizing for Analog Cells Through Reference Transistors
Auteur(s) :
Iskander, Ramy [Auteur]
Circuits Intégrés Numériques et Analogiques [CIAN]
Rosset-Louërat, Marie-Minerve [Auteur]
Circuits Intégrés Numériques et Analogiques [CIAN]
Kaiser, Andreas [Auteur]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
Circuits Intégrés Numériques et Analogiques [CIAN]
Rosset-Louërat, Marie-Minerve [Auteur]
Circuits Intégrés Numériques et Analogiques [CIAN]
Kaiser, Andreas [Auteur]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
Titre de la manifestation scientifique :
PRIME IEEE Conference on Ph.D. Research in MicroElectronics and Electronics Winner of the Bronze Leaf Certificate
Ville :
Otranto
Pays :
Italie
Date de début de la manifestation scientifique :
2006-06
Titre de l’ouvrage :
PRIME IEEE Conference on Ph.D. Research in MicroElectronics and Electronics Winner of the Bronze Leaf Certificate
Éditeur :
IEEE
Discipline(s) HAL :
Informatique [cs]
Résumé en anglais : [en]
In this paper, an algorithm for automatic sizing and operating point computation of hierarchical knowledge-based analog cells is presented. The algorithm assumes that an analog cell is described as a hierarchy of devices ...
Lire la suite >In this paper, an algorithm for automatic sizing and operating point computation of hierarchical knowledge-based analog cells is presented. The algorithm assumes that an analog cell is described as a hierarchy of devices and modules inside our dedicated framework CAIRO+. Within devices, the concept of the reference transistor is elaborated. The latter is used to construct device dependency graphs for each device. Module dependency graphs are constructed by merging graphs of all children modules and devices. Inside each device, the reference transistor controls the sizing and biasing of the whole device. It propagates electrical parameters to secondary transistors. The used propagation technique ensures that all the device constraints are satisfied by construction. The algorithm was used to size and bias a two-stage single-ended OTA amplifier. It proved to be successful in DC operating point calculation in the context of hierarchical knowledge-based framework.Lire moins >
Lire la suite >In this paper, an algorithm for automatic sizing and operating point computation of hierarchical knowledge-based analog cells is presented. The algorithm assumes that an analog cell is described as a hierarchy of devices and modules inside our dedicated framework CAIRO+. Within devices, the concept of the reference transistor is elaborated. The latter is used to construct device dependency graphs for each device. Module dependency graphs are constructed by merging graphs of all children modules and devices. Inside each device, the reference transistor controls the sizing and biasing of the whole device. It propagates electrical parameters to secondary transistors. The used propagation technique ensures that all the device constraints are satisfied by construction. The algorithm was used to size and bias a two-stage single-ended OTA amplifier. It proved to be successful in DC operating point calculation in the context of hierarchical knowledge-based framework.Lire moins >
Langue :
Anglais
Comité de lecture :
Oui
Audience :
Internationale
Vulgarisation :
Non
Source :