Title :

Modeling transistor level masking of soft errors in combinational circuits

Author(s) :

Alouani, Lihsen [Auteur correspondant]
COMmunications NUMériques - IEMN [COMNUM - IEMN]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
Niar, Smail [Auteur]
Laboratoire d'Automatique, de Mécanique et d'Informatique industrielles et Humaines - UMR 8201 [LAMIH]
El Hillali, Yassin [Auteur]
COMmunications NUMériques - IEMN [COMNUM - IEMN]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
Rivenq, Atika [Auteur]
COMmunications NUMériques - IEMN [COMNUM - IEMN]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]

Conference title :

2015 IEEE East-West Design and Test Symposium, EWDTS 2015

City :

Batumi

Country :

Etats-Unis d'Amérique

Start date of the conference :

2015-09-26

Publisher :

Institute of Electrical and Electronics Engineers Inc.

Publication date :

2016

English keyword(s) :

Semiconductor devices
Transistors
Circuit complexity
CMOS logic circuits
Hardware resources
Probabilistic modeling
Soft error masking
Technology scaling
Transistor level
Transistor size
Computer circuits
Error correction
Errors
Radiation hardening
Reconfigurable hardware

HAL domain(s) :

Sciences de l'ingénieur [physics]

English abstract : [en]

Technology scaling in modern electronic circuits shrinks the transistor size and dramatically increases the sensitivity of semiconductor devices to radiations. Consequently, soft errors emerged as a serious reliability ...
Show more >Technology scaling in modern electronic circuits shrinks the transistor size and dramatically increases the sensitivity of semiconductor devices to radiations. Consequently, soft errors emerged as a serious reliability threat in both sequential and combinational circuits. To accurately estimate Soft Error Rates (SERs) within combinational circuits, the impact of masking mechanisms should be considered and precisely modeled. In fact, overestimating SERs may lead to unnecessary hardware resources overhead as well as higher power consumption and circuit complexity. This paper examines the effect of logic gates architecture on the SERs in CMOS logic circuits. We consider the impact of the Transistor Level Masking (TLM) and propose a probabilistic model for both circuit and gate levels The experimentations show that the probability of soft error masking due to TLM mechanism can reach 100% for NAND gates, 45% for c17 ISCAS'85 benchmark and 47% for a simplified c6288 ISCAS'85 benchmark. © 2015 IEEE.Show less >

Language :

Anglais

Peer reviewed article :

Oui

Audience :

Internationale

Popular science :

Non

ANR Project :

RAILENIUM

Collections :

• Institut d'Électronique, de Microélectronique et de Nanotechnologie (IEMN) - UMR 8520

Source :

Harvested from HAL