Contention-free scheduling of PREM tasks on partitioned multicore platforms

Senoussaoui, Ikram; Zahaf, Houssam-Eddine; Lipari, Giuseppe; Benhaoua, Kamel

Type de document :

Autre communication scientifique (congrès sans actes - poster - séminaire...): Communication dans un congrès avec actes

Titre :

Contention-free scheduling of PREM tasks on partitioned multicore platforms

Auteur(s) :

Senoussaoui, Ikram [Auteur]
Centre de Recherche en Informatique, Signal et Automatique de Lille - UMR 9189 [CRIStAL]
Zahaf, Houssam-Eddine [Auteur]
Laboratoire des Sciences du Numérique de Nantes [LS2N]
Lipari, Giuseppe [Auteur]

Analyse symbolique et conception orientée composants pour des systèmes embarqués temps-réel modulaires [SYCOMORES]
Centre de Recherche en Informatique, Signal et Automatique de Lille - UMR 9189 [CRIStAL]
Benhaoua, Kamel [Auteur]
Université d'Oran 1 Ahmed Ben Bella [Oran]

Titre de la manifestation scientifique :

2022 IEEE 27th International Conference on Emerging Technologies and Factory Automation (ETFA)

Ville :

Stuttgart

Pays :

Allemagne

Date de début de la manifestation scientifique :

2022-09-06

Discipline(s) HAL :

Informatique [cs]

Résumé en anglais : [en]

Commercial-off-the-shelf (COTS) platforms feature several cores that share and contend for memory resources. In real-time system applications, it is of paramount importance to correctly estimate tight upper bounds to the ...
Lire la suite >Commercial-off-the-shelf (COTS) platforms feature several cores that share and contend for memory resources. In real-time system applications, it is of paramount importance to correctly estimate tight upper bounds to the delays due tomemory contention. However, without proper support from the hardware (e.g. a real-time bus scheduler), it is difficult to estimate such upper bounds.This work aims at avoiding contention for a set of tasks modeled using the Predictable Execution Model (PREM), i.e. each task execution is divided into a memory phase and a computation phase, on a hardware multicore architecture where each core has its private scratchpad memory and all cores share the main memory. We consider non-preemptive scheduling for memory phases, whereas computation phases are scheduled using partitioned preemptive EDF. In this work, we propose three novel approaches to avoid contention in memory phases: (i) a task-level time-triggered approach, (ii) job-level time-triggered approach, and (iii) on-line scheduling approach. We compare the proposed approaches against the state of the art using a set of synthetic experiments in terms of schedulability and analysis time. Furthermore, we implemented the different approaches on an Infineon AURIX TC397 multicore microcontroller and validated the proposed approaches using a set of tasks extracted from well-known benchmarks from the literature.Lire moins >

Langue :

Anglais

Comité de lecture :

Oui

Audience :

Internationale

Vulgarisation :

Non

Collections :

Centre de Recherche en Informatique, Signal et Automatique de Lille (CRIStAL) - UMR 9189

Source :

Harvested from HAL

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