Titre :

Multi-core versus Many-core Computing for Many-task Branch-and-Bound applied to Big Optimization Problems

Auteur(s) :

Melab, Nouredine [Auteur]
Optimisation de grande taille et calcul large échelle [BONUS]
Gmys, Jan [Auteur]
Optimisation de grande taille et calcul large échelle [BONUS]
Université de Mons / University of Mons [UMONS]
Mezmaz, Mohand [Auteur]
Université de Mons / University of Mons [UMONS]
Tuyttens, Daniel [Auteur]
Université de Mons / University of Mons [UMONS]

Titre de la revue :

Future Generation Computer Systems

Pagination :

20

Éditeur :

Elsevier

Date de publication :

2018-05-31

ISSN :

0167-739X

Mot(s)-clé(s) en anglais :

Coprocessor/Many-core
Muti-core
Parallel Branch-and-Bound
permutation Flow-Shop

Discipline(s) HAL :

Informatique [cs]/Calcul parallèle, distribué et partagé [cs.DC]
Computer Science [cs]/Operations Research [math.OC]

Résumé en anglais : [en]

On the road to exascale, coprocessors are increasingly becoming key building blocks of High Performance Computing platforms. In addition to their energy efficiency, these many-core devices boost the performance of multi-core ...
Lire la suite >On the road to exascale, coprocessors are increasingly becoming key building blocks of High Performance Computing platforms. In addition to their energy efficiency, these many-core devices boost the performance of multi-core processors. In this paper, we revisit the design and implementation of Branch-and-Bound (B&B) algorithms for multi-core processors and Intel Xeon Phi coprocessors considering the offload mode as well as the native one. In addition, two major parallel models are considered: the master-worker and the work pool models. We address several parallel computing issues including processor-coprocessor data transfer optimization and vectorization. The proposed approaches have been experimented using the Flow-Shop scheduling problem (FSP) and two hardware configurations equivalent in terms of energy consumption: Intel Xeon E5-2670 processor and Intel Xeon Phi 5110P coprocessor. The reported results show that: (1) the proposed vectorization mechanism reduces the execution time by 42.1% (resp. 21.2%) in the many-core (resp. multi-core) approach ; (2) the native mode allows a faster execution on MIC than the offload mode for all FSP problem instances ; (3) the many-core approach (offload or native) is in average twice faster than the multi-core approach ; (4) the work pool parallel model is more suited for many/multi-core B&B applied to FSP than the master-worker model becauseof its irregular nature.Lire moins >

Langue :

Anglais

Vulgarisation :

Non

Collections :

• Centre de Recherche en Informatique, Signal et Automatique de Lille (CRIStAL) - UMR 9189

Source :

Harvested from HAL