FPGA-based many-core System-on-Chip design
Document type :
Article dans une revue scientifique
Title :
FPGA-based many-core System-on-Chip design
Author(s) :
Baklouti, Mouna [Auteur]
Computer & Embedded Systems [CES Lab]
Marquet, Philippe [Auteur]
Dynamic Reconfigurable Massively Parallel Architectures and Languages [DREAMPAL]
Dekeyser, Jean-Luc [Auteur]
Dynamic Reconfigurable Massively Parallel Architectures and Languages [DREAMPAL]
Abid, Mohamed [Auteur]
Computer & Embedded Systems [CES Lab]
Computer & Embedded Systems [CES Lab]
Marquet, Philippe [Auteur]

Dynamic Reconfigurable Massively Parallel Architectures and Languages [DREAMPAL]
Dekeyser, Jean-Luc [Auteur]

Dynamic Reconfigurable Massively Parallel Architectures and Languages [DREAMPAL]
Abid, Mohamed [Auteur]
Computer & Embedded Systems [CES Lab]
Journal title :
Microprocessors and Microsystems: Embedded Hardware Design
Pages :
38
Publisher :
Elsevier
Publication date :
2015
ISSN :
0141-9331
HAL domain(s) :
Informatique [cs]
English abstract : [en]
Massively parallel architectures are proposed as a promising solution to speed up data-intensive applications and provide the required computational power. In particular, Single Instruction Multiple Data (SIMD) many-core ...
Show more >Massively parallel architectures are proposed as a promising solution to speed up data-intensive applications and provide the required computational power. In particular, Single Instruction Multiple Data (SIMD) many-core architec-tures have been adopted for multimedia and signal processing applications with massive amounts of data parallelism where both performance and flexible programmability are important metrics. However, this class of processors has faced many challenges due to its increasing fabrication cost and design complexity. Moreover, the increasing gap between design productivity and chip complexity requires new design methods. Nowadays, the recent evolution of silicon integration technology, on the one hand, and the wide usage of reusable Intellectual Property (IP) cores and FPGAs (Field Pro-grammable Gate Arrays), on the other hand, are attractive solutions to meet these challenges and reduce the time-to-market. The objective of this work is to study the performances of massively parallel SIMD on-chip architecturesShow less >
Show more >Massively parallel architectures are proposed as a promising solution to speed up data-intensive applications and provide the required computational power. In particular, Single Instruction Multiple Data (SIMD) many-core architec-tures have been adopted for multimedia and signal processing applications with massive amounts of data parallelism where both performance and flexible programmability are important metrics. However, this class of processors has faced many challenges due to its increasing fabrication cost and design complexity. Moreover, the increasing gap between design productivity and chip complexity requires new design methods. Nowadays, the recent evolution of silicon integration technology, on the one hand, and the wide usage of reusable Intellectual Property (IP) cores and FPGAs (Field Pro-grammable Gate Arrays), on the other hand, are attractive solutions to meet these challenges and reduce the time-to-market. The objective of this work is to study the performances of massively parallel SIMD on-chip architecturesShow less >
Language :
Anglais
Peer reviewed article :
Oui
Audience :
Internationale
Popular science :
Non
Collections :
Source :
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