Broadcast with mask on a Massively Parallel Processing on a Chip

Krichene, Hana; Baklouti, Mouna; Abid, Mohamed; Marquet, Philippe; Dekeyser, Jean-Luc

Type de document :

Autre communication scientifique (congrès sans actes - poster - séminaire...)

Titre :

Broadcast with mask on a Massively Parallel Processing on a Chip

Auteur(s) :

Krichene, Hana [Auteur]
Département de Génie Électrique de Sfax [ENIS] [CEM Lab - ENIS]
Contributions of the Data parallelism to real time [DART]
Baklouti, Mouna [Auteur]
Département de Génie Électrique de Sfax [ENIS] [CEM Lab - ENIS]
Abid, Mohamed [Auteur]
Département de Génie Électrique de Sfax [ENIS] [CEM Lab - ENIS]
Marquet, Philippe [Auteur]

Contributions of the Data parallelism to real time [DART]
Dekeyser, Jean-Luc [Auteur]
Contributions of the Data parallelism to real time [DART]

Date de publication :

2012

Discipline(s) HAL :

Informatique [cs]/Systèmes embarqués

Résumé en anglais : [en]

The delay of instructions broadcast has a significant impact on the performance of Single Instruction Multiple Data (SIMD) architecture. This is especially true for massively parallel processing Systems-on-Chip (mppSoC), ...
Lire la suite >The delay of instructions broadcast has a significant impact on the performance of Single Instruction Multiple Data (SIMD) architecture. This is especially true for massively parallel processing Systems-on-Chip (mppSoC), where the processing stage and that of setting up the communication mechanism need several clock periods. Subnetting is the strategy used to partition a single physical network into more than one smaller logical sub-networks (subnets). This technique better controls the broadcast instructions domain and the data traffic between network nodes. Furthermore, it allows to separate synchronous communications from asynchronous processing which maintains reliable communications and rapid processing through parallel processors. This paper describes the design of a communication model called broadcast with mask. This model is dedicated to mppSoC architecture with a huge number of processor elements because it maintains performances even when the number of processors increases. Simulation results and an FPGA implementation validate our approach.Lire moins >

Langue :

Anglais

Audience :

Non spécifiée

Vulgarisation :

Non

Collections :

Centre de Recherche en Informatique, Signal et Automatique de Lille (CRIStAL) - UMR 9189

Source :

Harvested from HAL

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