Scalable mpNoC for massively parallel systems - Design and implementation on FPGA

Baklouti, Mouna; Aydi, Yassine; Marquet, Philippe; Dekeyser, Jean-Luc; Abid, Mohamed

Document type :

Article dans une revue scientifique

DOI :

10.1016/j.sysarc.2010.04.001

Title :

Scalable mpNoC for massively parallel systems - Design and implementation on FPGA

Author(s) :

Baklouti, Mouna [Auteur]
Contributions of the Data parallelism to real time [DART]
Aydi, Yassine [Auteur]
Computer & Embedded Systems [CES Lab]
Marquet, Philippe [Auteur]

Laboratoire d'Informatique Fondamentale de Lille [LIFL]
Contributions of the Data parallelism to real time [DART]
Dekeyser, Jean-Luc [Auteur]
Laboratoire d'Informatique Fondamentale de Lille [LIFL]
Contributions of the Data parallelism to real time [DART]
Abid, Mohamed [Auteur]
Computer & Embedded Systems [CES Lab]

Journal title :

Journal of Systems Architecture

Pages :

278 - 292

Publisher :

Elsevier

Publication date :

2010

ISSN :

1383-7621

English keyword(s) :

Communication
FPGA
Network architecture
SIMD parallel processing
System on a Chip

HAL domain(s) :

Informatique [cs]/Systèmes embarqués

English abstract : [en]

The high chip-level integration enables the implementation of large-scale parallel processing architectures with 64 and more processing nodes on a single chip or on an FPGA device. These parallel systems require a ...
Show more >The high chip-level integration enables the implementation of large-scale parallel processing architectures with 64 and more processing nodes on a single chip or on an FPGA device. These parallel systems require a cost-effective yet high-performance interconnection scheme to provide the needed communications between processors. The massively parallel Network on Chip (mpNoC) was proposed to address the demand for parallel irregular communications for massively parallel processing System on Chip (mppSoC). Targeting FPGA-based design, an efficient mpNoC low level RTL implementation is proposed taking into account design constraints. The proposed network is designed as an FPGA based Intellectual Property (IP) able to be configured in different communication modes. It can communicate between processors and also perform parallel I/O data transfer which is clearly a key issue in an SIMD system. The mpNoC RTL implementation presents good performances in terms of area, throughput and power consumption which are important metrics targeting an on chip implementation. mpNoC is a flexible architecture that is suitable for use in FPGA-based parallel systems. This paper introduces the basic mppSoC architecture. It mainly focuses on the mpNoC flexible IP based design and its implementation on FPGA. The integration of mpNoC in mppSoC is also described. Implementation results on a Stratix II FPGA device are given for three data-parallel applications ran on mppSoC. The obtained good performances justify the effectiveness of the proposed parallel network. It is shown that the mpNoC is a lightweight parallel network making it suitable for both small as well as large FPGA-based parallel systems.Show less >

Language :

Anglais

Peer reviewed article :

Oui

Audience :

Internationale

Popular science :

Non

Comment :

Special Issue on HW/SW Co-Design: Systems and Networks on Chip

Collections :

Centre de Recherche en Informatique, Signal et Automatique de Lille (CRIStAL) - UMR 9189

Source :

Harvested from HAL

Files

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