Title :

A Digital Delay Line with Coarse/Fine tuning through Gate/Body biasing in 28nm FDSOI

Author(s) :

Sourikopoulos, Ilias [Auteur]
Frappé, Antoine [Auteur]
Microélectronique Silicium - IEMN [MICROELEC SI - IEMN]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
Cathelin, Andreia [Auteur]
Clavier, Laurent [Auteur]
Circuits Systèmes Applications des Micro-ondes - IEMN [CSAM - IEMN]
Ecole nationale supérieure Mines-Télécom Lille Douai [IMT Lille Douai]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
Kaiser, Andreas [Auteur]
Microélectronique Silicium - IEMN [MICROELEC SI - IEMN]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]

Conference title :

46th European Solid-State Device Research Conference (ESSDERC) / 42nd European Solid-State Circuits Conference (ESSCIRC)

City :

Lausanne

Country :

Suisse

Start date of the conference :

2016-09-12

Book title :

46th European Solid-State Device Research Conference (ESSDERC) / 42nd European Solid-State Circuits Conference (ESSCIRC)

Journal title :

Proceedings 42nd European Solid-State Circuits Conference, ESSCIRC 2016

Publisher :

IEEE

Publication date :

2016

English keyword(s) :

Delay element
FDSOI
body-biasing
digital delay line

HAL domain(s) :

Sciences de l'ingénieur [physics]

English abstract : [en]

This paper discusses the design and characterization of a programmable digital delay line. The core of the proposed architecture is a thyristor-type delay element featuring the capability for coarse/fine tuning without ...
Show more >This paper discusses the design and characterization of a programmable digital delay line. The core of the proposed architecture is a thyristor-type delay element featuring the capability for coarse/fine tuning without using any additional hardware. This is made possible by taking advantage of body biasing features available in 28nm FDSOI CMOS. Body biasing offers unique performance characteristics, notably a very low sensitivity to the biasing voltage. The prototype delay line was designed featuring thermometer-code multi-stage activation and gate/body biasing control. A delay range from 560ps to 16.13ns is exhibited for the delay line with a 2GS/s input stream. The unit delay cell exhibits fs/mV sensitivity combined with an order of magnitude larger delay dynamic range and an energy efficiency of only 12.5 fJ/event.Show less >

Language :

Anglais

Peer reviewed article :

Oui

Audience :

Internationale

Popular science :

Non

Collections :

• Institut d'Électronique, de Microélectronique et de Nanotechnologie (IEMN) - UMR 8520

Source :

Harvested from HAL