Title :

Heartbeat-based synchronization scheme for the human intranet: modeling and analysis

Author(s) :

Benarrouch, Robin [Auteur]
Berkeley Wireless Research Center [Berkeley] [BWRC]
STMicroelectronics [Crolles] [ST-CROLLES]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
Moin, Ali [Auteur]
Berkeley Wireless Research Center [Berkeley] [BWRC]
Solt, Flavien [Auteur]
Berkeley Wireless Research Center [Berkeley] [BWRC]
STMicroelectronics [Crolles] [ST-CROLLES]
École polytechnique [X]
Frappé, Antoine [Auteur]
Microélectronique Silicium - IEMN [MICROELEC SI - IEMN]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
Cathelin, Andreia [Auteur]
STMicroelectronics [Crolles] [ST-CROLLES]
Kaiser, Andreas [Auteur]
Microélectronique Silicium - IEMN [MICROELEC SI - IEMN]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
Rabaey, Jan [Auteur]
Berkeley Wireless Research Center [Berkeley] [BWRC]

Conference title :

2020 IEEE International Symposium on Circuits and Systems (ISCAS)

City :

Sevilla

Country :

Espagne

Start date of the conference :

2020-10-12

Journal title :

Proceedings of the 52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020

Publisher :

IEEE

Publication date :

2020-10

English keyword(s) :

Body Area Network (BAN)
Synchronization
Heartbeat
Duty-cycled receiver

HAL domain(s) :

Sciences de l'ingénieur [physics]/Micro et nanotechnologies/Microélectronique

English abstract : [en]

Sharing a common clock signal among the nodes is crucial for communication in synchronized networks. This work presents a heartbeat-based synchronization scheme for body-worn nodes. The principles of this coordination ...
Show more >Sharing a common clock signal among the nodes is crucial for communication in synchronized networks. This work presents a heartbeat-based synchronization scheme for body-worn nodes. The principles of this coordination technique combined with a puncture-based communication method are introduced. Theoretical models of the hardware blocks are presented, outlining the impact of their specifications on the system. Moreover, we evaluate the synchronization efficiency in simulation and compare with a duty-cycled receiver topology. Improvement in power consumption of at least 26% and tight latency control are highlighted at no cost on the channel availability.Show less >

Language :

Anglais

Peer reviewed article :

Oui

Audience :

Internationale

Popular science :

Non

Comment :

ORAL

Collections :

• Institut d'Électronique, de Microélectronique et de Nanotechnologie (IEMN) - UMR 8520

Source :

Harvested from HAL