Title :

All-digital transmitter architecture based on two-path parallel 1-bit high pass filtering DACs

Author(s) :

Gebreyohannes, Fikre Tsigabu [Auteur]
Circuits Intégrés Numériques et Analogiques [CIAN]
Frappe, Antoine [Auteur]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
Microélectronique Silicium - IEMN [MICROELEC SI - IEMN]
Cathelin, Philippe [Auteur]
STMicroelectronics [Crolles] [ST-CROLLES]
Kaiser, Andreas [Auteur]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
Microélectronique Silicium - IEMN [MICROELEC SI - IEMN]
Cathelin, Andreia [Auteur]

Journal title :

IEEE Transactions on Circuits and Systems I: Regular Papers

Pages :

3956-3969

Publisher :

IEEE

Publication date :

2018-11

ISSN :

1549-8328

English keyword(s) :

time-interleaving
high pass FIR DACs
parallel DACs
Index Terms-Digital transmitter

HAL domain(s) :

Sciences de l'ingénieur [physics]/Micro et nanotechnologies/Microélectronique
Informatique [cs]/Architectures Matérielles [cs.AR]

English abstract : [en]

This paper presents a novel transmitter architecture which is tailored for low power, all-digital, and high speed implementation. It is based on two-path parallel digital-to-analog converters (DAC) which are driven by 180 ...
Show more >This paper presents a novel transmitter architecture which is tailored for low power, all-digital, and high speed implementation. It is based on two-path parallel digital-to-analog converters (DAC) which are driven by 180 • phase-shifted clocks. The architecture operates in high pass mode and extends the output carrier frequency up to half the DAC clock rate. To decrease the number of analog unit current cells in the converter, a low-pass-modulator is used. Since the modulator also converts the input resolution to 1-bit, an inherently-linear digital-to-analog conversion is realized by embedding filtering in the DAC. Furthermore, the finite impulse response DAC transfer function is designed to cancel the-modulator quantization noise. Simulation results at system level demonstrate the robustness of the architecture against random coefficient mismatches, and its suitability for broadband transmissions. The error vector magnitude of the quadrature output is simulated for up to 15% random coefficient mismatch and it maintains a value below −22 dB even when the input signal bandwidths vary from 20 MHz (64-subcarrier OFDM) to 160 MHz (512-subcarrier OFDM). Experimental results are presented to discuss the validity of the proposed all-digital transmitter architecture and to highlight the challenges of implementing it in advanced CMOS nodes.Show less >

Language :

Anglais

Popular science :

Non

ANR Project :

WiGig FlExible TraNsceiver ADvanced SYstem

Collections :

• Institut d'Électronique, de Microélectronique et de Nanotechnologie (IEMN) - UMR 8520

Source :

Harvested from HAL