Titre :

Normally-off AlGaN/GaN MOS-HEMT using ultra-thin Al_0.45 Ga_0.55N barrier layer

Auteur(s) :

Chakroun, Ahmed [Auteur]
Institut Interdisciplinaire d'Innovation Technologique [Sherbrooke] [3IT]
Laboratoire Nanotechnologies Nanosystèmes [LN2 ]
Jaouad, Abdelatif [Auteur]
Institut Interdisciplinaire d'Innovation Technologique [Sherbrooke] [3IT]
Laboratoire Nanotechnologies Nanosystèmes [LN2 ]
Bouchilaoun, Meriem [Auteur]
Arenas, Osvaldo [Auteur]
Soltani, Ali [Auteur]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
Maher, Hassan [Auteur]
Institut Interdisciplinaire d'Innovation Technologique [Sherbrooke] [3IT]
Laboratoire Nanotechnologies Nanosystèmes [LN2 ]
OMMIC

Titre de la revue :

Physica Status Solidi A (applications and materials science)

Éditeur :

Wiley

Date de publication :

2017-08

ISSN :

1862-6300

Mot(s)-clé(s) en anglais :

AlGaN
digital etching
GaN
high electron mobility transistors
metal-oxide-semiconductor structures
passivation

Discipline(s) HAL :

Sciences de l'ingénieur [physics]

Résumé en anglais : [en]

In this work, we report on the fabrication of a normally‐off AlGaN/GaN Metal–Oxide–Semiconductor High Electron Mobility Transistor (MOS‐HEMT) using an ultra‐thin Al0.45Ga0.55N barrier layer. The AlGaN barrier was thinned ...
Lire la suite >In this work, we report on the fabrication of a normally‐off AlGaN/GaN Metal–Oxide–Semiconductor High Electron Mobility Transistor (MOS‐HEMT) using an ultra‐thin Al0.45Ga0.55N barrier layer. The AlGaN barrier was thinned down to 1 nm using a digital etching process (Oxidation/Etching) and was followed by a PECVD deposition technique of a 7 nm thick SiOx layer used as gate insulator. Thanks to the thin AlGaN barrier layer (4 nm), only a few digital etching cycles are required to shift the threshold voltage toward positive values. The fabricated normally‐off device exhibits a pinch‐off voltage of +1.1 V, a maximum IDS current of 460 mA mm−1 at VGS = +5 V, an On‐state resistance (RON) of 7.8 Ω · mm and an ION/IOFF ratio higher than 109. Moreover, the pulsed IDS–VDS and capacitance–voltage (C–V) curves versus frequency confirm that there is no damage induced by the digital etching process.Lire moins >

Langue :

Anglais

Comité de lecture :

Oui

Audience :

Internationale

Vulgarisation :

Non

Collections :

• Institut d'Électronique, de Microélectronique et de Nanotechnologie (IEMN) - UMR 8520

Source :

Harvested from HAL