Title :

Electronic transport mechanisms in scaled gate-all-around silicon nanowire transistor arrays

Author(s) :

Clement, N. [Auteur]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
Han, X.L. [Auteur]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
Larrieu, Guilhem [Auteur]
Équipe Matériaux et Procédés pour la Nanoélectronique [LAAS-MPN]

Journal title :

Applied Physics Letters

Pages :

263504

Publisher :

American Institute of Physics

Publication date :

2013

ISSN :

0003-6951

HAL domain(s) :

Sciences de l'ingénieur [physics]/Micro et nanotechnologies/Microélectronique

English abstract : [en]

Low-frequency noise is used to study the electronic transport in arrays of 14 nm gate length vertical silicon nanowire devices. We demonstrate that, even at such scaling, the electrostatic control of the gate-all-around ...
Show more >Low-frequency noise is used to study the electronic transport in arrays of 14 nm gate length vertical silicon nanowire devices. We demonstrate that, even at such scaling, the electrostatic control of the gate-all-around is sufficient in the sub-threshold voltage region to confine charges in the heart of the wire, and the extremely low noise level is comparable to that of high quality epitaxial layers. Although contact noise can already be a source of poor transistor operation above threshold voltage for few nanowires, nanowire parallelization drastically reduces its impact.Show less >

Language :

Anglais

Peer reviewed article :

Oui

Audience :

Internationale

Popular science :

Non

Collections :

• Institut d'Électronique, de Microélectronique et de Nanotechnologie (IEMN) - UMR 8520

Source :

Harvested from HAL