Title :

Register file reliability enhancement through adjacent narrow-width exploitation.

Author(s) :

Ahangari, Hamzeh [Auteur]
Universite Bilkent [Ankara]
Alouani, Ihsen [Auteur]
COMmunications NUMériques - IEMN [COMNUM - IEMN]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
Özturk, Özcan [Auteur]
Universite Bilkent [Ankara]
Niar, Smail [Auteur]
Laboratoire d'Automatique, de Mécanique et d'Informatique industrielles et Humaines - UMR 8201 [LAMIH]
Rivenq, Atika [Auteur]
COMmunications NUMériques - IEMN [COMNUM - IEMN]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]

Conference title :

2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS)

City :

Istanbul

Country :

Turquie

Start date of the conference :

2016-04-12

Book title :

2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS)

Publisher :

IEEE

English keyword(s) :

"Registers"
Radio frequency
Computer architecture
Microprocessors
Integrated circuit reliability
SRAM cells

HAL domain(s) :

Informatique [cs]
Sciences de l'ingénieur [physics]

English abstract : [en]

Due to the increasing vulnerability of CMOS circuits, new generations of microprocessors require an inevitable focus on reliability issues. As the Register File (RF) constitutes a critical element within the processor ...
Show more >Due to the increasing vulnerability of CMOS circuits, new generations of microprocessors require an inevitable focus on reliability issues. As the Register File (RF) constitutes a critical element within the processor pipeline, it is mandatory to enhance the RF reliability to develop fault tolerant architectures. This paper proposes Adjacent Register Hardened RF (ARH), a new RF architecture that exploits the adjacent byte-level narrow-width values for hardening registers at runtime. Registers are paired together by some special switches referred to as joiners. Dummy sign bits of each register are used to keep redundant data of its counterpart register. We use 7T/14T SRAM cell [6] to combine redundant bits together to make a single bit cell which is, by far, more resilient against faults. Our simulations show that with 3% to 12% power overhead and 10% to 20% increase in area, in comparison to baseline RF, we can obtain up to 80% reduction in soft error rate (SER).Show less >

Language :

Anglais

Peer reviewed article :

Oui

Audience :

Internationale

Popular science :

Non

Collections :

• Institut d'Électronique, de Microélectronique et de Nanotechnologie (IEMN) - UMR 8520

Source :

Harvested from HAL