Improving off-state capacitance of SOI-CMOS ...
Document type :
Communication dans un congrès avec actes
Title :
Improving off-state capacitance of SOI-CMOS RF switches: how good are air microcavities?
Author(s) :
Gheysens, Daniel [Auteur]
STMicroelectronics [Crolles] [ST-CROLLES]
Fleury, Alain [Auteur]
STMicroelectronics [Crolles] [ST-CROLLES]
Monfray, Stéphane [Auteur]
STMicroelectronics [Crolles] [ST-CROLLES]
Gianesello, Frédéric [Auteur]
STMicroelectronics
Cathelin, Philippe [Auteur]
STMicroelectronics [Crolles] [ST-CROLLES]
Robillard, Jean-François [Auteur]
Microélectronique Silicium - IEMN [MICROELEC SI - IEMN]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
Troadec, David [Auteur]
Centrale de Micro Nano Fabrication - IEMN [CMNF - IEMN]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
Dubois, Emmanuel [Auteur]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
Microélectronique Silicium - IEMN [MICROELEC SI - IEMN]
STMicroelectronics [Crolles] [ST-CROLLES]
Fleury, Alain [Auteur]
STMicroelectronics [Crolles] [ST-CROLLES]
Monfray, Stéphane [Auteur]
STMicroelectronics [Crolles] [ST-CROLLES]
Gianesello, Frédéric [Auteur]
STMicroelectronics
Cathelin, Philippe [Auteur]
STMicroelectronics [Crolles] [ST-CROLLES]
Robillard, Jean-François [Auteur]

Microélectronique Silicium - IEMN [MICROELEC SI - IEMN]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
Troadec, David [Auteur]

Centrale de Micro Nano Fabrication - IEMN [CMNF - IEMN]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
Dubois, Emmanuel [Auteur]

Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
Microélectronique Silicium - IEMN [MICROELEC SI - IEMN]
Conference title :
IEEE 53rd European Solid-State Device Research Conference, ESSDERC
City :
Lisbon
Country :
Portugal
Start date of the conference :
2023-09-11
Book title :
Proceedings of the IEEE 53rd European Solid-State Device Research Conference, ESSDERC
Publisher :
IEEE
English keyword(s) :
RF switch
Air microcavities
CMOS
SOI
Off-state capacitance
Vapor phase selective etching
Air microcavities
CMOS
SOI
Off-state capacitance
Vapor phase selective etching
HAL domain(s) :
Sciences de l'ingénieur [physics]
English abstract : [en]
This paper investigates the reduction of the off-state capacitance (COFF) of SOI-CMOS RF switches induced by the introduction of air microcavity in the back-end interconnection network. A detailed methodology combining ...
Show more >This paper investigates the reduction of the off-state capacitance (COFF) of SOI-CMOS RF switches induced by the introduction of air microcavity in the back-end interconnection network. A detailed methodology combining electromagnetic and semiconductor transport simulations is used to separately evaluate the respective contributions of the interconnects and junction capacitances. A baseline switch and an optimized version of the same are studied to evaluate their ability to take advantage of air microcavities. Simulations show a reduction of 73 fF/mm regardless of the switch structure considered, resulting in a 24.6% and 30.6% improvement in COFF for baseline and optimized switches, respectively, bringing the optimized version to a 60fs record Ron × Coff. This concept was experimentally implemented using a partial etch process that resulted in a reduction of 21.7 fF/mm, i.e., 7.2%. Finally, the implementation of a more isotropic and selective etching process using HF in vapor phase is shown to approach the optimal configuration of air microcavities.Show less >
Show more >This paper investigates the reduction of the off-state capacitance (COFF) of SOI-CMOS RF switches induced by the introduction of air microcavity in the back-end interconnection network. A detailed methodology combining electromagnetic and semiconductor transport simulations is used to separately evaluate the respective contributions of the interconnects and junction capacitances. A baseline switch and an optimized version of the same are studied to evaluate their ability to take advantage of air microcavities. Simulations show a reduction of 73 fF/mm regardless of the switch structure considered, resulting in a 24.6% and 30.6% improvement in COFF for baseline and optimized switches, respectively, bringing the optimized version to a 60fs record Ron × Coff. This concept was experimentally implemented using a partial etch process that resulted in a reduction of 21.7 fF/mm, i.e., 7.2%. Finally, the implementation of a more isotropic and selective etching process using HF in vapor phase is shown to approach the optimal configuration of air microcavities.Show less >
Language :
Anglais
Peer reviewed article :
Oui
Audience :
Internationale
Popular science :
Non
Source :
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