Exploring HLS Optimizations for Efficient ...
Type de document :
Communication dans un congrès avec actes
Titre :
Exploring HLS Optimizations for Efficient Stereo Matching Hardware Implementation
Auteur(s) :
Ali, Karim Mohamed Abedallah [Auteur]
Laboratoire d'Automatique, de Mécanique et d'Informatique industrielles et Humaines - UMR 8201 [LAMIH]
Ben Atitallah, Rabie [Auteur]
Laboratoire d'Automatique, de Mécanique et d'Informatique industrielles et Humaines - UMR 8201 [LAMIH]
Fakhfakh, Nizar [Auteur]
Dekeyser, Jean-Luc [Auteur]
Centre de Recherche en Informatique, Signal et Automatique de Lille - UMR 9189 [CRIStAL]
Laboratoire d'Automatique, de Mécanique et d'Informatique industrielles et Humaines - UMR 8201 [LAMIH]
Ben Atitallah, Rabie [Auteur]
Laboratoire d'Automatique, de Mécanique et d'Informatique industrielles et Humaines - UMR 8201 [LAMIH]
Fakhfakh, Nizar [Auteur]
Dekeyser, Jean-Luc [Auteur]
Centre de Recherche en Informatique, Signal et Automatique de Lille - UMR 9189 [CRIStAL]
Titre de la manifestation scientifique :
13th International Symposium on Applied Reconfigurable Computing (ARC 2017)
Ville :
Delft
Pays :
Pays-Bas
Date de début de la manifestation scientifique :
2017-04-03
Mot(s)-clé(s) en anglais :
FPGA
High level synthesis
Stereo matching algorithms
High level synthesis
Stereo matching algorithms
Discipline(s) HAL :
Informatique [cs]/Architectures Matérielles [cs.AR]
Résumé en anglais : [en]
Nowadays, FPGA technology offers a tremendous number of logic cells on a single chip. Digital design for such huge hardware resources under time-to-market constraint urged the evolution of High Level Synthesis (HLS) tools. ...
Lire la suite >Nowadays, FPGA technology offers a tremendous number of logic cells on a single chip. Digital design for such huge hardware resources under time-to-market constraint urged the evolution of High Level Synthesis (HLS) tools. In this work, we will explore several HLS optimization steps in order to improve the system performance. Different design choices are obtained from our exploration such that an efficient implementation is selected based on given system constraints (resource utilization, power consumption, execution time, ...). Our exploration methodology is illustrated through a case study considering a Multi-Window Sum of Absolute Difference stereo matching algorithm. We implemented our design using Xilinx Zynq ZC706 FPGA evaluation board for gray images of size \(640\times 480\).Lire moins >
Lire la suite >Nowadays, FPGA technology offers a tremendous number of logic cells on a single chip. Digital design for such huge hardware resources under time-to-market constraint urged the evolution of High Level Synthesis (HLS) tools. In this work, we will explore several HLS optimization steps in order to improve the system performance. Different design choices are obtained from our exploration such that an efficient implementation is selected based on given system constraints (resource utilization, power consumption, execution time, ...). Our exploration methodology is illustrated through a case study considering a Multi-Window Sum of Absolute Difference stereo matching algorithm. We implemented our design using Xilinx Zynq ZC706 FPGA evaluation board for gray images of size \(640\times 480\).Lire moins >
Langue :
Anglais
Comité de lecture :
Oui
Audience :
Internationale
Vulgarisation :
Non
Collections :
Source :