Circuit Merging versus Dynamic Partial Reconfiguration -The HoMade Implementation

Perier, Jean; Chouchene, Wissem; Dekeyser, Jean-Luc

Document type :

Article dans une revue scientifique

Title :

Circuit Merging versus Dynamic Partial Reconfiguration -The HoMade Implementation

Author(s) :

Perier, Jean [Auteur correspondant]
Dynamic Reconfigurable Massively Parallel Architectures and Languages [DREAMPAL]
Chouchene, Wissem [Auteur]
Dynamic Reconfigurable Massively Parallel Architectures and Languages [DREAMPAL]
Dekeyser, Jean-Luc [Auteur]
Dynamic Reconfigurable Massively Parallel Architectures and Languages [DREAMPAL]

Journal title :

i-manager's Journal on Embedded Systems(JES)

Publisher :

i-manager Publications

Publication date :

2016

ISSN :

2278-7895

English keyword(s) :

FPGA
partial dynamic reconfiguration
circuit merging
softcore

HAL domain(s) :

Informatique [cs]
Informatique [cs]/Architectures Matérielles [cs.AR]

English abstract : [en]

One goal of reconfiguration is to save power and occupied resources. In this paper we compare two different kinds of reconfiguration available on field-programmable gate arrays (FPGA) and we discuss their pros and cons. ...
Show more >One goal of reconfiguration is to save power and occupied resources. In this paper we compare two different kinds of reconfiguration available on field-programmable gate arrays (FPGA) and we discuss their pros and cons. The first method that we study is circuit merging. This type of reconfiguration methods consists in sharing common resources between different circuits. The second method that we explore is dynamic partial reconfiguration (DPR). It is specific to some FPGA, allowing well defined reconfigurable parts to be modified during run-time. We show that DPR, when available, has good and more predictable result in terms of occupied area. There is still a huge overhead in term of time and power consumption during the reconfiguration phase. Therefore we show that circuit merging remains an interesting solution on FPGA because it is not vendor specific and the reconfiguration time is around a clock cycle. Besides, good merging algorithms exist even-though FPGA physical synthesis flow makes it hard to predict the real performance of the merged circuit during the optimization. We establish our comparison in the context of the HoMade processor.Show less >

Language :

Anglais

Peer reviewed article :

Oui

Audience :

Internationale

Popular science :

Non

Collections :

Centre de Recherche en Informatique, Signal et Automatique de Lille (CRIStAL) - UMR 9189

Source :

Harvested from HAL

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