High breakdown voltage and low buffer ...
Type de document :
Compte-rendu et recension critique d'ouvrage
DOI :
Titre :
High breakdown voltage and low buffer trapping in superlattice GaN-on-silicon heterostructures for high voltage applications
Auteur(s) :
Tajalli, Alaleh [Auteur]
Università degli Studi di Padova = University of Padua [Unipd]
Meneghini, Matteo [Auteur]
Besendörfer, Sven [Auteur]
Meneghesso, Gaudenzio [Auteur]
Abid, Idriss [Auteur]
WIde baNd gap materials and Devices - IEMN [WIND - IEMN]
Püsche, Roland [Auteur]
Derluyn, Joff [Auteur]
Kabouche, Riad [Auteur]
Degroote, Stefan [Auteur]
Germain, Marianne [Auteur]
Meissner, Elke [Auteur]
Zanoni, Enrico [Auteur]
Medjdoub, Farid [Auteur]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
WIde baNd gap materials and Devices - IEMN [WIND - IEMN]
Università degli Studi di Padova = University of Padua [Unipd]
Meneghini, Matteo [Auteur]
Besendörfer, Sven [Auteur]
Meneghesso, Gaudenzio [Auteur]
Abid, Idriss [Auteur]
WIde baNd gap materials and Devices - IEMN [WIND - IEMN]
Püsche, Roland [Auteur]
Derluyn, Joff [Auteur]
Kabouche, Riad [Auteur]
Degroote, Stefan [Auteur]
Germain, Marianne [Auteur]
Meissner, Elke [Auteur]
Zanoni, Enrico [Auteur]
Medjdoub, Farid [Auteur]
![refId](/themes/Mirage2//images/idref.png)
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
WIde baNd gap materials and Devices - IEMN [WIND - IEMN]
Titre de la revue :
Materials
Pagination :
4271
Éditeur :
MDPI
Date de publication :
2020-09-25
ISSN :
1996-1944
Mot(s)-clé(s) en anglais :
GaN
high-electron-mobility transistor (HEMT)
trapping effect back-gating analysis
high-electron-mobility transistor (HEMT)
trapping effect back-gating analysis
Discipline(s) HAL :
Sciences de l'ingénieur [physics]
Résumé en anglais : [en]
The aim of this work is to demonstrate high breakdown voltage and low buffer trapping in superlattice GaN-on-Silicon heterostructures for high voltage applications. To this aim, we compared two structures, one based on a ...
Lire la suite >The aim of this work is to demonstrate high breakdown voltage and low buffer trapping in superlattice GaN-on-Silicon heterostructures for high voltage applications. To this aim, we compared two structures, one based on a step-graded (SG) buffer (reference structure), and another based on a superlattice (SL). In particular, we show that: (i) the use of an SL allows us to push the vertical breakdown voltage above 1500 V on a 5 µm stack, with a simultaneous decrease in vertical leakage current, as compared to the reference GaN-based epi-structure using a thicker buffer thickness. This is ascribed to the better strain relaxation, as confirmed by X-Ray Diffraction data, and to a lower clustering of dislocations, as confirmed by Defect Selective Etching and Cathodoluminescence mappings. (ii) SL-based samples have significantly lower buffer trapping, as confirmed by substrate ramp measurements. (iii) Backgating transient analysis indicated that traps are located below the two-dimensional electron gas, and are related to C N defects. (iv) The signature of these traps is significantly reduced on devices with SL. This can be explained by the lower vertical leakage (filling of acceptors via electron injection) or by the slightly lower incorporation of C in the SL buffer, due to the slower growth process. SL-based buffers therefore represent a viable solution for the fabrication of high voltage GaN transistors on silicon substrate, and for the simultaneous reduction of trapping processes.Lire moins >
Lire la suite >The aim of this work is to demonstrate high breakdown voltage and low buffer trapping in superlattice GaN-on-Silicon heterostructures for high voltage applications. To this aim, we compared two structures, one based on a step-graded (SG) buffer (reference structure), and another based on a superlattice (SL). In particular, we show that: (i) the use of an SL allows us to push the vertical breakdown voltage above 1500 V on a 5 µm stack, with a simultaneous decrease in vertical leakage current, as compared to the reference GaN-based epi-structure using a thicker buffer thickness. This is ascribed to the better strain relaxation, as confirmed by X-Ray Diffraction data, and to a lower clustering of dislocations, as confirmed by Defect Selective Etching and Cathodoluminescence mappings. (ii) SL-based samples have significantly lower buffer trapping, as confirmed by substrate ramp measurements. (iii) Backgating transient analysis indicated that traps are located below the two-dimensional electron gas, and are related to C N defects. (iv) The signature of these traps is significantly reduced on devices with SL. This can be explained by the lower vertical leakage (filling of acceptors via electron injection) or by the slightly lower incorporation of C in the SL buffer, due to the slower growth process. SL-based buffers therefore represent a viable solution for the fabrication of high voltage GaN transistors on silicon substrate, and for the simultaneous reduction of trapping processes.Lire moins >
Langue :
Anglais
Vulgarisation :
Non
Projet Européen :
Source :
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