Power-efficient reliable register file for ...
Type de document :
Compte-rendu et recension critique d'ouvrage
Titre :
Power-efficient reliable register file for aggressive-environment applications
Auteur(s) :
Alouani, Lihsen [Auteur correspondant]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
COMmunications NUMériques - IEMN [COMNUM - IEMN]
INSA Institut National des Sciences Appliquées Hauts-de-France [INSA Hauts-De-France]
Ahangari, Hamzeh [Auteur]
Bilkent University [Ankara]
Özturk, Özcan [Auteur]
Bilkent University [Ankara]
Niar, Smail [Auteur]
Laboratoire d'Automatique, de Mécanique et d'Informatique industrielles et Humaines - UMR 8201 [LAMIH]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
COMmunications NUMériques - IEMN [COMNUM - IEMN]
INSA Institut National des Sciences Appliquées Hauts-de-France [INSA Hauts-De-France]
Ahangari, Hamzeh [Auteur]
Bilkent University [Ankara]
Özturk, Özcan [Auteur]
Bilkent University [Ankara]
Niar, Smail [Auteur]
Laboratoire d'Automatique, de Mécanique et d'Informatique industrielles et Humaines - UMR 8201 [LAMIH]
Titre de la revue :
IET Computers & Digital Techniques
Pagination :
1-8
Éditeur :
Institution of Engineering and Technology
Date de publication :
2020-01
ISSN :
1751-8601
Mot(s)-clé(s) en anglais :
embedded systems
microprocessor chips
integrated circuit reliability
power aware computing
floating point arithmetic
reliability
flip-flops
power-efficient reliable register file
aggressive-environment applications
on-board data processing
reduced power budget
serious design challenge
embedded system manufacturers
embedded processors
aggressive environments
error hardening
critical element
processor pipeline
fault immune computing systems
authors propose
RF architecture
adjacent byte-level narrow-width values
integer registers
nonutilised bits
counterpart register
floating point critical bits
low power budget
normal operating conditions
highly aggressive operating conditions
floating point RF reliability enhancement techniques
adjacent register hardened RF
microprocessor chips
integrated circuit reliability
power aware computing
floating point arithmetic
reliability
flip-flops
power-efficient reliable register file
aggressive-environment applications
on-board data processing
reduced power budget
serious design challenge
embedded system manufacturers
embedded processors
aggressive environments
error hardening
critical element
processor pipeline
fault immune computing systems
authors propose
RF architecture
adjacent byte-level narrow-width values
integer registers
nonutilised bits
counterpart register
floating point critical bits
low power budget
normal operating conditions
highly aggressive operating conditions
floating point RF reliability enhancement techniques
adjacent register hardened RF
Discipline(s) HAL :
Sciences de l'ingénieur [physics]
Informatique [cs]
Informatique [cs]/Intelligence artificielle [cs.AI]
Informatique [cs]/Réseaux et télécommunications [cs.NI]
Sciences de l'ingénieur [physics]/Traitement du signal et de l'image [eess.SP]
Sciences de l'ingénieur [physics]/Electronique
Informatique [cs]
Informatique [cs]/Intelligence artificielle [cs.AI]
Informatique [cs]/Réseaux et télécommunications [cs.NI]
Sciences de l'ingénieur [physics]/Traitement du signal et de l'image [eess.SP]
Sciences de l'ingénieur [physics]/Electronique
Résumé en anglais : [en]
In a context of increasing demands for on-board data processing, insuring reliability under reduced power budget is a serious design challenge for embedded system manufacturers. Particularly, embedded processors in aggressive ...
Lire la suite >In a context of increasing demands for on-board data processing, insuring reliability under reduced power budget is a serious design challenge for embedded system manufacturers. Particularly, embedded processors in aggressive environments need to be designed with error hardening as a primary goal, not an afterthought. As Register File (RF) is a critical element within the processor pipeline, enhancing RF reliability is mandatory to design fault immune computing systems. This study proposes integer and floating point RF reliability enhancement techniques. Specifically, the authors propose Adjacent Register Hardened RF, a new RF architecture that exploits the adjacent byte-level narrow-width values for hardening integer registers at runtime. Registers are paired together by special switches referred to as joiners and non-utilised bits of each register are exploited to enhance the reliability of its counterpart register. Moreover, they suggest sacrificing the least significant bits of the Mantissa to enhance the reliability of the floating point critical bits, namely, Exponent and Sign bits. The authors' results show that with a low power budget compared to state of the art techniques, they achieve better results under both normal and highly aggressive operating conditions.Lire moins >
Lire la suite >In a context of increasing demands for on-board data processing, insuring reliability under reduced power budget is a serious design challenge for embedded system manufacturers. Particularly, embedded processors in aggressive environments need to be designed with error hardening as a primary goal, not an afterthought. As Register File (RF) is a critical element within the processor pipeline, enhancing RF reliability is mandatory to design fault immune computing systems. This study proposes integer and floating point RF reliability enhancement techniques. Specifically, the authors propose Adjacent Register Hardened RF, a new RF architecture that exploits the adjacent byte-level narrow-width values for hardening integer registers at runtime. Registers are paired together by special switches referred to as joiners and non-utilised bits of each register are exploited to enhance the reliability of its counterpart register. Moreover, they suggest sacrificing the least significant bits of the Mantissa to enhance the reliability of the floating point critical bits, namely, Exponent and Sign bits. The authors' results show that with a low power budget compared to state of the art techniques, they achieve better results under both normal and highly aggressive operating conditions.Lire moins >
Langue :
Anglais
Vulgarisation :
Non
Source :