Titre :

A modeling front-end for seamless design and generation of context-aware Dynamically Reconfigurable Systems-on-Chip

Auteur(s) :

Ochoa-Ruiz, Gilberto [Auteur]
Laboratoire Electronique, Informatique et Image [UMR6306] [Le2i]
Wattebled, Pamela [Auteur]
Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance [Lab-STICC]
Touiza, Maamar [Auteur]
Laboratoire Electronique, Informatique et Image [UMR6306] [Le2i]
de Lamotte, Florent [Auteur]
Lab-STICC_UBS_CACS_MOCS
Bourennane, El-Bay [Auteur]
Laboratoire Electronique, Informatique et Image [UMR6306] [Le2i]
Meftali, Samy [Auteur]
Université de Lille
Dekeyser, Jean-Luc [Auteur]
Dynamic Reconfigurable Massively Parallel Architectures and Languages [DREAMPAL]
Diguet, Jean-Philippe [Auteur]
Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance [Lab-STICC]

Titre de la revue :

Journal of Parallel and Distributed Computing

Pagination :

1-19

Éditeur :

Elsevier

Date de publication :

2018-02

ISSN :

0743-7315

Mot(s)-clé(s) en anglais :

System-on-Chip
Reconfigurable systems
UML MARTE
Bistream relocation
IP-XACT
management
Context-aware

Discipline(s) HAL :

Sciences de l'ingénieur [physics]/Electronique

Résumé en anglais : [en]

In this paper, we present a Model Driven Engineering (MDE) methodology for facilitating the modeling of the partial reconfiguration process, and for implementing Dynamic Reconfigurable System-on-Chip (DRSoC). The rationale ...
Lire la suite >In this paper, we present a Model Driven Engineering (MDE) methodology for facilitating the modeling of the partial reconfiguration process, and for implementing Dynamic Reconfigurable System-on-Chip (DRSoC). The rationale for this approach is to provide a modeling front-end that enables to visually compose a hardware platform, containing heterogeneous components, using both static and context-management hardware wrappers. A model transformations engine (MTE) processes the high-level models to obtain the inputs for the Xilinx dynamic partial reconfiguration (DPR) design flow, with the benefit of better exploiting and reusing the designer intentions regarding the allocation of tasks into reconfigurable areas. Furthermore, the automatic synthesis of a reconfiguration controller (RecOS) with context-management and task relocation capabilities is supported in this version of our tool. The latter feature is possible due to the integration of relocation tool OORBIT into the design chain, but we point out at other avenues of research. We present a case study in which we assess the benefits of the methodology and present a thorough analysis of the reconfiguration costs associated with the context and relocation management, showing speedups of 1.5x over other solutions.Lire moins >

Langue :

Anglais

Vulgarisation :

Non

Collections :

• Centre de Recherche en Informatique, Signal et Automatique de Lille (CRIStAL) - UMR 9189

Source :

Harvested from HAL