AFFORDe: Automatic Allocation and Floorplanning for SPMD Architecture

Chouchene, Wissem; Ben Atitallah, Rabie; Dekeyser, Jean-Luc

Type de document :

Communication dans un congrès avec actes

DOI :

10.1109/MCSoC.2016.38

Titre :

AFFORDe: Automatic Allocation and Floorplanning for SPMD Architecture

Auteur(s) :

Chouchene, Wissem [Auteur]
Dynamic Reconfigurable Massively Parallel Architectures and Languages [DREAMPAL]
Ben Atitallah, Rabie [Auteur]
Laboratoire d'Automatique, de Mécanique et d'Informatique industrielles et Humaines - UMR 8201 [LAMIH]
Dekeyser, Jean-Luc [Auteur]
Dynamic Reconfigurable Massively Parallel Architectures and Languages [DREAMPAL]

Titre de la manifestation scientifique :

MCSOC 2016 - 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip

Ville :

Lyon

Pays :

France

Date de début de la manifestation scientifique :

2016-09-21

Discipline(s) HAL :

Informatique [cs]/Architectures Matérielles [cs.AR]

Résumé en anglais : [en]

Nowadays, Field Programmable Gate Arrays (FPGAs) platforms offer a high density to allow designing Multi Processor-based System on Chip. SPMD (Single Program Multiple Data) is a massively parallel execution model based on ...
Lire la suite >Nowadays, Field Programmable Gate Arrays (FPGAs) platforms offer a high density to allow designing Multi Processor-based System on Chip. SPMD (Single Program Multiple Data) is a massively parallel execution model based on the assembly of a given number of homogeneous Processing Elements (PEs). This model is often relaying on Master/Slaves architecture composed by a Master PE that manages the parallel execution of a set of identical slave PEs. Furthermore, Dynamic Partial Reconfiguration (DPR) feature allows such computing system to be reconfigured on the fly for a given application requirement. Given the growing number of PEs in Master/Slaves architecture, it is difficult to estimate the time of specification and design during the phase of allocation and floorplanning of Partial Reconfigurable Regions (PRRs) because it is still performed manually. In this work, we present AFFORDe, a tool enable to automate the Xilinx DPR flow for SPMD architecture that allows parsing the resource requirements of the static and the dynamically reconfigurable parts to perform an automatic floorplanning. The floorplanning is based on a Heuristic Algorithm for Automatic Floorplanning in SPMD Architectures (HAAFSA). This tool is used to generate a configuration file that allows floorplanning of reconfigurable regions in an automatic way of a given Master/Slaves configuration. Experimental results show the effectiveness of our tool to increase the design productivity for dynamically reconfigurable SPMD-based architecture.Lire moins >

Langue :

Anglais

Comité de lecture :

Oui

Audience :

Internationale

Vulgarisation :

Non

Collections :

Centre de Recherche en Informatique, Signal et Automatique de Lille (CRIStAL) - UMR 9189

Source :

Harvested from HAL

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