Titre :

Enabling partially reconfigurable IP cores parameterisation and integration using MARTE and IP-XACT

Auteur(s) :

Ochoa-Ruiz, Gilberto [Auteur]
Laboratoire Electronique, Informatique et Image [UMR6306] [Le2i]
Labbani, Ouassila [Auteur]
Laboratoire Electronique, Informatique et Image [UMR6306] [Le2i]
Bourennane, El-Bay [Auteur]
Laboratoire Electronique, Informatique et Image [UMR6306] [Le2i]
Cherif, Sana [Auteur]
Laboratoire d'Informatique Fondamentale de Lille [LIFL]
Contributions of the Data parallelism to real time [DART]
Meftali, Samy [Auteur]
Inria Lille - Nord Europe
Dekeyser, Jean-Luc [Auteur]
Laboratoire d'Informatique Fondamentale de Lille [LIFL]
Contributions of the Data parallelism to real time [DART]

Titre de la manifestation scientifique :

2012 23rd IEEE International Symposium on Rapid System Prototyping (RSP)

Pays :

Finlande

Date de début de la manifestation scientifique :

2012-10-12

Titre de l’ouvrage :

Rapid System Prototyping (RSP), 2012 23rd IEEE International Symposium on

Date de publication :

2012-10-12

Discipline(s) HAL :

Informatique [cs]/Systèmes embarqués

Résumé en anglais : [en]

This paper presents a framework which facilitates the parameterization and integration of IP cores into partially reconfigurable SoC platforms, departing from a high-level of abstraction. The approach is based in a ...
Lire la suite >This paper presents a framework which facilitates the parameterization and integration of IP cores into partially reconfigurable SoC platforms, departing from a high-level of abstraction. The approach is based in a Model-Driven Engineering (MDE) methodology, which exploits two widely used standards for Systems-on-Chip specification, MARTE and IP-XACT. The presented work deals with the deployment level of the MDE approach, in which the abstract components of the platform are first linked to the lower level IP-XACT counterparts. At this phase, information for parameterization and integration is readily available, and a synthesizable model can be obtained from the generated IP-XACT through model transformations. We detail how certain IP-XACT objects are exploited in our approach; the emphasis is given to the generation of IP cores in a Xilinx EDK environment. We provide a case study in which a complete DPR platform is modeled in MARTE and implemented in a FPGA.Lire moins >

Langue :

Anglais

Comité de lecture :

Oui

Audience :

Internationale

Vulgarisation :

Non

Collections :

• Centre de Recherche en Informatique, Signal et Automatique de Lille (CRIStAL) - UMR 9189

Source :

Harvested from HAL