Targeting Reconfigurable FPGA based SoCs ...
Type de document :
Article dans une revue scientifique: Article original
Titre :
Targeting Reconfigurable FPGA based SoCs using the MARTE UML profile: from high abstraction levels to code generation
Auteur(s) :
Quadri, Imran Rafiq [Auteur]
Contributions of the Data parallelism to real time [DART]
Yu, Huafeng [Auteur]
Synchronous programming for the trusted component-based engineering of embedded systems and mission-critical systems [ESPRESSO]
Gamatié, Abdoulaye [Auteur]
Laboratoire d'Informatique Fondamentale de Lille [LIFL]
Contributions of the Data parallelism to real time [DART]
Meftali, Samy [Auteur]
Laboratoire d'Informatique Fondamentale de Lille [LIFL]
Contributions of the Data parallelism to real time [DART]
Dekeyser, Jean-Luc [Auteur]
Laboratoire d'Informatique Fondamentale de Lille [LIFL]
Contributions of the Data parallelism to real time [DART]
Rutten, Eric [Auteur]
System architecture for reflective distributed computing environments [SARDES]
Contributions of the Data parallelism to real time [DART]
Yu, Huafeng [Auteur]
Synchronous programming for the trusted component-based engineering of embedded systems and mission-critical systems [ESPRESSO]
Gamatié, Abdoulaye [Auteur]
Laboratoire d'Informatique Fondamentale de Lille [LIFL]
Contributions of the Data parallelism to real time [DART]
Meftali, Samy [Auteur]
Laboratoire d'Informatique Fondamentale de Lille [LIFL]
Contributions of the Data parallelism to real time [DART]
Dekeyser, Jean-Luc [Auteur]
Laboratoire d'Informatique Fondamentale de Lille [LIFL]
Contributions of the Data parallelism to real time [DART]
Rutten, Eric [Auteur]
System architecture for reflective distributed computing environments [SARDES]
Titre de la revue :
International Journal of Embedded Systems
Pagination :
18 p
Éditeur :
Inderscience
Date de publication :
2010-09-16
ISSN :
1741-1068
Discipline(s) HAL :
Informatique [cs]/Systèmes embarqués
Résumé en anglais : [en]
As SoC design complexity is escalating to new heights, there is a critical need to find adequate approaches and tools to handle SoC co-design aspects. Additionally, modern reconfigurable SoCs offer advantages over classical ...
Lire la suite >As SoC design complexity is escalating to new heights, there is a critical need to find adequate approaches and tools to handle SoC co-design aspects. Additionally, modern reconfigurable SoCs offer advantages over classical SoCs as they integrate adaptivity features to cope with mutable design requirements and environment needs. This paper presents a novel approach to address system adaptivity and reconfigurability. A generic model of reactive control is presented in a SoC codesign framework: Gaspard. Afterwards, control integration at different levels of the framework is illustrated for both functional specification and FPGA synthesis. The presented work is based on Model-Driven Engineering and the UML MARTE profile proposed by Object Management Group, for modeling and analysis of real-time embedded systems. The paper thus presents a complete design flow to move from high level MARTE models to code generation, for implementation of dynamically reconfigurable SoCs.Lire moins >
Lire la suite >As SoC design complexity is escalating to new heights, there is a critical need to find adequate approaches and tools to handle SoC co-design aspects. Additionally, modern reconfigurable SoCs offer advantages over classical SoCs as they integrate adaptivity features to cope with mutable design requirements and environment needs. This paper presents a novel approach to address system adaptivity and reconfigurability. A generic model of reactive control is presented in a SoC codesign framework: Gaspard. Afterwards, control integration at different levels of the framework is illustrated for both functional specification and FPGA synthesis. The presented work is based on Model-Driven Engineering and the UML MARTE profile proposed by Object Management Group, for modeling and analysis of real-time embedded systems. The paper thus presents a complete design flow to move from high level MARTE models to code generation, for implementation of dynamically reconfigurable SoCs.Lire moins >
Langue :
Anglais
Comité de lecture :
Oui
Audience :
Internationale
Vulgarisation :
Non
Collections :
Source :
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