MARTE based modeling approach for Partial ...
Type de document :
Communication dans un congrès avec actes
Titre :
MARTE based modeling approach for Partial Dynamic Reconfigurable FPGAs
Auteur(s) :
Quadri, Imran Rafiq [Auteur]
Contributions of the Data parallelism to real time [DART]
Meftali, Samy [Auteur]
Laboratoire d'Informatique Fondamentale de Lille [LIFL]
Contributions of the Data parallelism to real time [DART]
Dekeyser, Jean-Luc [Auteur]
Laboratoire d'Informatique Fondamentale de Lille [LIFL]
Contributions of the Data parallelism to real time [DART]
Contributions of the Data parallelism to real time [DART]
Meftali, Samy [Auteur]

Laboratoire d'Informatique Fondamentale de Lille [LIFL]
Contributions of the Data parallelism to real time [DART]
Dekeyser, Jean-Luc [Auteur]

Laboratoire d'Informatique Fondamentale de Lille [LIFL]
Contributions of the Data parallelism to real time [DART]
Titre de la manifestation scientifique :
Sixth IEEE Workshop on Embedded Systems for Real-time Multimedia (ESTIMedia 2008)
Ville :
Atlanta
Pays :
Etats-Unis d'Amérique
Date de début de la manifestation scientifique :
2008-10-23
Date de publication :
2008-10-23
Discipline(s) HAL :
Informatique [cs]/Systèmes embarqués
Résumé en anglais : [en]
As System-on-Chip (SoC) architectures become pivotal for designing embedded systems, the SoC design complexity continues to increase exponentially necessitating the need to find new design methodologies. In this paper we ...
Lire la suite >As System-on-Chip (SoC) architectures become pivotal for designing embedded systems, the SoC design complexity continues to increase exponentially necessitating the need to find new design methodologies. In this paper we present a novel SoC co-design methodology based on Model Driven Engineering using the MARTE (Modeling and Analysis of Real-time and Embedded Systems) standard. This methodology is utilized to model fine grain reconfigurable architectures such as FPGAs and extends the standard to integrate new features such as Partial Dynamic Reconfiguration supported by modern FPGAs. The goal is to carry out modeling at a high abstraction level expressed in UML (Unified Modeling Language) and following transformations of these models, automatically generate the code necessary for FPGA implementation.Lire moins >
Lire la suite >As System-on-Chip (SoC) architectures become pivotal for designing embedded systems, the SoC design complexity continues to increase exponentially necessitating the need to find new design methodologies. In this paper we present a novel SoC co-design methodology based on Model Driven Engineering using the MARTE (Modeling and Analysis of Real-time and Embedded Systems) standard. This methodology is utilized to model fine grain reconfigurable architectures such as FPGAs and extends the standard to integrate new features such as Partial Dynamic Reconfiguration supported by modern FPGAs. The goal is to carry out modeling at a high abstraction level expressed in UML (Unified Modeling Language) and following transformations of these models, automatically generate the code necessary for FPGA implementation.Lire moins >
Langue :
Anglais
Comité de lecture :
Oui
Audience :
Internationale
Vulgarisation :
Non
Collections :
Source :
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