Title :

A fully flexible circuit implementation of clique-based neural networks in 65-nm CMOS
[Invited]

Author(s) :

Larras, Benoit [Auteur]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
Microélectronique Silicium - IEMN [MICROELEC SI - IEMN]
Chollet, Paul [Auteur]
Département Electronique [ELEC]
Lahuec, Cyril [Auteur]
Département Electronique [ELEC]
Seguin, Fabrice [Auteur]
Département Electronique [ELEC]
Arzel, Matthieu [Auteur]
Département Electronique [ELEC]

Journal title :

IEEE Transactions on Circuits and Systems I: Regular Papers

Pages :

1-12

Publisher :

IEEE

Publication date :

2018-12-14

ISSN :

1549-8328

English keyword(s) :

Neurons
Synapses
Biological neural networks
Silicon
Leakage currents
Complexity theory
Neural networks circuit
clique-based neural networks
analog/mixed-signal circuit
iterative circuit structure
classification circuit

HAL domain(s) :

Sciences de l'ingénieur [physics]/Electronique
Sciences du Vivant [q-bio]/Ingénierie biomédicale
Sciences du Vivant [q-bio]/Médecine humaine et pathologie/Cardiologie et système cardiovasculaire
Sciences de l'ingénieur [physics]

English abstract : [en]

Clique-based neural networks implement low-complexity functions working with a reduced connectivity between neurons. Thus, they address very specific applications operating with a very low-energy budget. However, the ...
Show more >Clique-based neural networks implement low-complexity functions working with a reduced connectivity between neurons. Thus, they address very specific applications operating with a very low-energy budget. However, the implementation in the state of the art is not flexible and a fabricated circuit is only usable in a unique use case. Besides, the silicon area of hardwired circuits grows exponentially with the number of implemented neurons that is prohibitive for embedded applications. This paper proposes a flexible and iterative neural architecture capable of implementing multiple types of clique-based neural networks of up to 3968 neurons. The circuit has been integrated in an ST 65-nm CMOS ASIC and occupies a 0.21-mm 2 silicon surface area. The proper functioning of the circuit is illustrated using two application cases: a keyword recovery application and an electrocardiogram classification. The neurons outputs are updated 83 ns after a stimulation, and a neuron needs an energy of 115 fJ to propagate a change at the input to its output.Show less >

Language :

Anglais

Popular science :

Non

ANR Project :

Unité de pré-traitement pour systèmes intégrés à faible énergie

Collections :

• Institut d'Électronique, de Microélectronique et de Nanotechnologie (IEMN) - UMR 8520

Source :

Harvested from HAL