Title :

An ultra-low power iterative clique-based neural network integrated in 65-nm CMOS

Author(s) :

Chollet, Paul [Auteur]
Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance [Lab-STICC]
Département Electronique [ELEC]
Larras, Benoit [Auteur]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
Lahuec, Cyril [Auteur]
Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance [Lab-STICC]
Département Electronique [ELEC]
Seguin, Fabrice [Auteur]
Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance [Lab-STICC]
Département Electronique [ELEC]
Arzel, Matthieu [Auteur]
Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance [Lab-STICC]
Département Electronique [ELEC]

Conference title :

NEWCAS 2017 : 15th IEEE International New Circuits and Systems Conference

City :

Strasbourg

Country :

France

Start date of the conference :

2017-06-25

Book title :

Proceedings NEWCAS 2017 : 15th IEEE International New Circuits and Systems Conference

Publication date :

2017

English keyword(s) :

Analogue IC design
Ultra low power
CMOS analogue integrated circuits
Neural Networks

HAL domain(s) :

Sciences de l'ingénieur [physics]/Electronique
Sciences de l'ingénieur [physics]/Traitement du signal et de l'image [eess.SP]

English abstract : [en]

Clique-based neural networks are less complex than commonly used neural network models. They have a limited connectivity and are composed of simple functions. They are thus adapted to implement neuro-inspired computation ...
Show more >Clique-based neural networks are less complex than commonly used neural network models. They have a limited connectivity and are composed of simple functions. They are thus adapted to implement neuro-inspired computation units operating under severe energy constraints. This paper shows an ST 65-nm CMOS ASIC implementation for a 30-neuron cliquebased neural network circuit. With a 1V power supply and 300nA unitary current, the neuron energy consumption is only 17fJ per synaptic event. The network occupies 41,820um² silicon area.Show less >

Language :

Anglais

Peer reviewed article :

Oui

Audience :

Internationale

Popular science :

Non

Collections :

• Institut d'Électronique, de Microélectronique et de Nanotechnologie (IEMN) - UMR 8520

Source :

Harvested from HAL