Title :

Systematic Offset Detection and Evaluation Using Hierarchical Graph-Based Sizing and Biasing

Author(s) :

Iskander, Ramy [Auteur]
Circuits Intégrés Numériques et Analogiques [CIAN]
Kaiser, Andreas [Auteur]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
Louërat, Marie-Minerve [Auteur]
Circuits Intégrés Numériques et Analogiques [CIAN]

Conference title :

14th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)

City :

Marrackech

Country :

Maroc

Start date of the conference :

2007-12

Book title :

14th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)

Publisher :

IEEE

HAL domain(s) :

Informatique [cs]

English abstract : [en]

A hierarchical graph-based sizing and biasing method of analog circuits has been previously developed. However, conflicts appear in dependency graphs generated by our method due to the large number of degrees of freedom ...
Show more >A hierarchical graph-based sizing and biasing method of analog circuits has been previously developed. However, conflicts appear in dependency graphs generated by our method due to the large number of degrees of freedom in analog design. Therefore, an enhanced method is presented that automatically detects conflicts and resolves them by inserting systematic offset voltages as additional degrees of freedom into the graph. During graph evaluation, a systematic offset is evaluated as the voltage difference between conflicting nodes, which can be eliminated by transposing it to the inputs of the circuit. As an example, we have successfully applied our method to the sizing of a single-ended two-stage operational amplifier.Show less >

Language :

Anglais

Peer reviewed article :

Oui

Audience :

Internationale

Popular science :

Non

Collections :

• Institut d'Électronique, de Microélectronique et de Nanotechnologie (IEMN) - UMR 8520

Source :

Harvested from HAL