• English
    • français
  • Help
  •  | 
  • Contact
  •  | 
  • About
  •  | 
  • Login
  • HAL portal
  •  | 
  • Pages Pro
  • EN
  •  / 
  • FR
View Item 
  •   LillOA Home
  • Liste des unités
  • Institut d'Électronique, de Microélectronique et de Nanotechnologie (IEMN) - UMR 8520
  • View Item
  •   LillOA Home
  • Liste des unités
  • Institut d'Électronique, de Microélectronique et de Nanotechnologie (IEMN) - UMR 8520
  • View Item
JavaScript is disabled for your browser. Some features of this site may not work without it.

CNTFET design of a multiple-port ternary ...
  • BibTeX
  • CSV
  • Excel
  • RIS

Document type :
Article dans une revue scientifique
DOI :
10.1016/j.mejo.2021.105076
Title :
CNTFET design of a multiple-port ternary register file
Author(s) :
Mohammaden, Amr [Auteur]
Fouda, Mohammed [Auteur]
Alouani, Ihsen [Auteur]
COMmunications NUMériques - IEMN [COMNUM - IEMN]
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 [IEMN]
Said, Lobna [Auteur]
Radwan, Ahmed [Auteur]
Journal title :
Microelectronics Journal
Pages :
105076
Publisher :
Elsevier
Publication date :
2021-07
ISSN :
0026-2692
English keyword(s) :
Ternary logic gates
CNTFET
Latch
Flip flop
Dynamic
D-latch
CNTEFT
HAL domain(s) :
Sciences de l'ingénieur [physics]
English abstract : [en]
Ternary number system offers higher information processing within the same number of digits when compared to binary systems. Such advantage motivated the development of ternary processing units especially with CNTFET which ...
Show more >
Ternary number system offers higher information processing within the same number of digits when compared to binary systems. Such advantage motivated the development of ternary processing units especially with CNTFET which offers better power and delay results compared to CMOS-based realization. In this paper, we propose a variety of circuit realizations for the ternary memory elements that are needed in any processor including ternary D-latch, and ternary D-flip-flop. These basic building blocks are then used to design a ternary register file with multiple read and write ports. This paper is an attempt to investigate the performance aspects of using ternary RF to open the gate of more contributions and research in the direction of full ternary computer architecture. The proposed designs have been compared in terms of power, area, and latency at different supply voltages and operating temperatures.Show less >
Language :
Anglais
Peer reviewed article :
Oui
Audience :
Internationale
Popular science :
Non
Collections :
  • Institut d'Électronique, de Microélectronique et de Nanotechnologie (IEMN) - UMR 8520
Source :
Harvested from HAL
Université de Lille

Mentions légales
Université de Lille © 2017