Titre :

Memory-processor co-scheduling for real-time tasks on network-on-chip manycore architectures

Auteur(s) :

Benchehida, Chawki [Auteur]
Université d'Oran 1 Ahmed Ben Bella [Oran]
Analyse symbolique et conception orientée composants pour des systèmes embarqués temps-réel modulaires [SYCOMORES]
Kamel Benhaoua, Mohammed [Auteur]
Université Mustapha Stambouli de Mascara [Algérie] = University Mustapha Stambouli [Mascara, Algeria] [UMSM]
Université d'Oran 1 Ahmed Ben Bella [Oran]
Zahaf, Houssam [Auteur]
Laboratoire des Sciences du Numérique de Nantes [LS2N]
Lipari, Giuseppe [Auteur]
Analyse symbolique et conception orientée composants pour des systèmes embarqués temps-réel modulaires [SYCOMORES]

Titre de la revue :

International Journal of High Performance Systems Architecture (IJHPSA)

Pagination :

1-11

Éditeur :

InderScience Publisher

Date de publication :

2022-01-31

ISSN :

1751-6528

Discipline(s) HAL :

Informatique [cs]/Systèmes embarqués
Informatique [cs]/Système d'exploitation [cs.OS]
Informatique [cs]/Architectures Matérielles [cs.AR]

Résumé en anglais : [en]

The Network-on-Chip (NoC) provides a viable solution to bus-contention problems in classical Multi/Many core architectures. However, NoC complex design requires particular attention to support the execution of real-time ...
Lire la suite >The Network-on-Chip (NoC) provides a viable solution to bus-contention problems in classical Multi/Many core architectures. However, NoC complex design requires particular attention to support the execution of real-time workloads. In fact, it is necessary to take into account task-to-core allocation and inter-task communication, so that all timing constraints are respected. The problem is more complex when considering task-to-main-memory communication, as the main memory is off-chip and usually connected to the network edges, within the 2D-Mesh topology, which generates a particular additional pattern of traffic. In this paper, we tackle these problems by considering the allocation of tasks and inter-task communications, and memory-to-task communications (modeled using Directed Acyclic Graphs DAGs) at the same time, rather than separating them, as it has been addressed in the literature of real-time systems. This problem is highly combinatorial, therefore our approach transforms it at each step, to a simpler problem until reaching the classical single-core scheduling problem. The goal is to find a trade-off between the problem combinatorial explosion and the loss of generality when simplifying the problem. We study the effectiveness of the proposed approaches using a large set of synthetic experiments.Lire moins >

Langue :

Anglais

Comité de lecture :

Oui

Audience :

Internationale

Vulgarisation :

Non

Collections :

• Centre de Recherche en Informatique, Signal et Automatique de Lille (CRIStAL) - UMR 9189

Source :

Harvested from HAL